[v1, 1/2] riscv: vector: clear V-reg in the first-use trap

[Björn Töpel]

Andy Chiu <andy.chiu at sifive.com> writes:

> If there is no context switch happens after we enable V for a process,
> then we return to user space with whatever left on the CPU's V registers
> accessible to the process. The leaked data could belong to another
> process's V-context saved from last context switch, impacting process's
> confidentiality on the system.
>
> To prevent this from happening, we clear V registers by restoring
> zero'd V context after turining on V.
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>

Reviewed-by: Björn Töpel <bjorn at rivosinc.com>