[PATCH] RISC-V: fixup ISA string parser merge conflict

[Palmer Dabbelt]

On Thu, 22 Jun 2023 15:18:43 PDT (-0700), Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
>
> Commit 6589450fa2e3 ("Merge patch series "ISA string parser cleanups"")
> has interacted poorly with commit 16252e018a30 ("Merge patch series
> "RISC-V: Export Zba, Zbb to usermode via hwprobe""), as there were some
> semantic conflicts between the former which added more users of the
> "this_isa" bitmap which the latter removed.
>
> Fixes: 6589450fa2e3 ("Merge patch series "ISA string parser cleanups"")
> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
> ---
> As promised, feel free to squash ;)

Thanks, I will ;)

> ---
>  arch/riscv/kernel/cpufeature.c | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 8ecd6f0af213..bdcf460ea53d 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -131,7 +131,6 @@ void __init riscv_fill_hwcap(void)
>  	for_each_possible_cpu(cpu) {
>  		struct riscv_isainfo *isainfo = &hart_isa[cpu];
>  		unsigned long this_hwcap = 0;
> -		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
>
>  		if (acpi_disabled) {
>  			node = of_cpu_device_node_get(cpu);
> @@ -162,7 +161,6 @@ void __init riscv_fill_hwcap(void)
>  		 */
>  		isa += 4;
>
> -		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
>  		while (*isa) {
>  			const char *ext = isa++;
>  			const char *ext_end = isa;
> @@ -323,8 +321,8 @@ void __init riscv_fill_hwcap(void)
>  		 * Linux requires the following extensions, so we may as well
>  		 * always set them.
>  		 */
> -		set_bit(RISCV_ISA_EXT_ZICSR, this_isa);
> -		set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa);
> +		set_bit(RISCV_ISA_EXT_ZICSR, isainfo->isa);
> +		set_bit(RISCV_ISA_EXT_ZIFENCEI, isainfo->isa);
>
>  		/*
>  		 * These ones were as they were part of the base ISA when the
> @@ -332,8 +330,8 @@ void __init riscv_fill_hwcap(void)
>  		 * unconditionally where `i` is in riscv,isa on DT systems.
>  		 */
>  		if (acpi_disabled) {
> -			set_bit(RISCV_ISA_EXT_ZICNTR, this_isa);
> -			set_bit(RISCV_ISA_EXT_ZIHPM, this_isa);
> +			set_bit(RISCV_ISA_EXT_ZICNTR, isainfo->isa);
> +			set_bit(RISCV_ISA_EXT_ZIHPM, isainfo->isa);
>  		}
>
>  		/*