[PATCH v2] RISC-V: Document that V registers are clobbered on syscalls

[Björn Töpel]

Palmer Dabbelt <palmer at rivosinc.com> writes:

> This is included in the ISA manual, but it's pretty common for bits of
> the ISA manual that are actually ABI to change.  So let's document it
> explicitly.
>
> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> ---
> Changes since v1 <20230614163534.18668-1-palmer at rivosinc.com>:
>
> * Remove the code change, just update the documentation.  We might still
>   want to do something in the code, but that's still under discussion so
>   let's get the docs sorted out for now.
> ---
>  Documentation/riscv/vector.rst | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/riscv/vector.rst b/Documentation/riscv/vector.rst
> index 48f189d79e41..96f0fedece73 100644
> --- a/Documentation/riscv/vector.rst
> +++ b/Documentation/riscv/vector.rst
> @@ -130,3 +130,9 @@ processes in form of sysctl knob:
>  
>      Modifying the system default enablement status does not affect the enablement
>      status of any existing process of thread that do not make an execve() call.
> +
> +3.  Vector Register State Across System Calls
> +---------------------------------------------
> +
> +As indicated by version 1.0 of the V extension, vector registers are clobbered
> +by system calls.

Maybe add a reference to the spec [1]?

Regardless if that is added, or not:
Reviewed-by: Björn Töpel <bjorn at rivosinc.com>

[1] https://github.com/riscv/riscv-v-spec/blob/master/calling-convention.adoc