[PATCH v9 0/6] Add non-coherent DMA support for AX45MP

[Conor Dooley]

On Wed, Jun 14, 2023 at 11:47:53AM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Hi All,
> 
> non-coherent DMA support for AX45MP
> ====================================
> 
> On the Andes AX45MP core, cache coherency is a specification option so it
> may not be supported. In this case DMA will fail. To get around with this
> issue this patch series does the below:
> 
> 1] Andes alternative ports is implemented as errata which checks if the IOCP
> is missing and only then applies to CMO errata. One vendor specific SBI EXT
> (ANDES_SBI_EXT_IOCP_SW_WORKAROUND) is implemented as part of errata.
> 
> Below are the configs which Andes port provides (and are selected by RZ/Five):
>       - ERRATA_ANDES
>       - ERRATA_ANDES_CMO
> 
> OpenSBI patch supporting ANDES_SBI_EXT_IOCP_SW_WORKAROUND SBI can be found here,
> https://patchwork.ozlabs.org/project/opensbi/patch/20230317140357.14819-1-prabhakar.mahadev-lad.rj@bp.renesas.com/
> 
> 2] Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
> block that allows dynamic adjustment of memory attributes in the runtime.
> It contains a configurable amount of PMA entries implemented as CSR
> registers to control the attributes of memory locations in interest.
> OpenSBI configures the PMA regions as required and creates a reserve memory
> node and propagates it to the higher boot stack.
> 
> Currently OpenSBI (upstream) configures the required PMA region and passes
> this a shared DMA pool to Linux.
> 
>     reserved-memory {
>         #address-cells = <2>;
>         #size-cells = <2>;
>         ranges;
> 
>         pma_resv0 at 58000000 {
>             compatible = "shared-dma-pool";
>             reg = <0x0 0x58000000 0x0 0x08000000>;
>             no-map;
>             linux,dma-default;
>         };
>     };
> 
> The above shared DMA pool gets appended to Linux DTB so the DMA memory
> requests go through this region.
> 
> 3] We provide callbacks to synchronize specific content between memory and
> cache.
> 
> 4] RZ/Five SoC selects the below configs
>         - AX45MP_L2_CACHE
>         - DMA_GLOBAL_POOL
>         - ERRATA_ANDES
>         - ERRATA_ANDES_CMO
> 
> ----------x---------------------x--------------------x---------------x--------------
> 
> Note,
> - Ive used GCC 12.2.0 for compilation
> - Tested all the IP blocks on RZ/Five which use DMA
> - Patch series is dependent on the series from Arnd,
>   https://patchwork.kernel.org/project/linux-riscv/cover/20230327121317.4081816-1-arnd@kernel.org/.
>   (Ive rebased Arnd's series on v6.4-rc-1)
> - Patches applies on top of palmer/for-next (255b34d799dd)
> - Ive pushed the complete tree here https://github.com/prabhakarlad/linux/tree/rzfive-cmo-v9
> - Previously the function pointer approach was NAKed by Christoph Hellwig but based on the discussion
>   on #riscv Ive implemented this approach.

Last time around you wanted someone to try this on a d1. I have done &
seems to work just as well as it did before. For where it is relevant:
Tested-by: Conor Dooley <conor.dooley at microchip.com> # tyre-kicking on a d1

Cheers,
Conor.
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