From: Conor Dooley <conor.dooley at microchip.com>
With that out of the way, here are some cleanups for our riscv,isa
handling.
Here are some bits that were discussed with Drew on the "should we
allow caps" threads that I have now created patches for:
- splitting of riscv_of_processor_hartid() into two distinct functions,
one for use purely during early boot, prior to the establishment of
the possible-cpus mask & another to fit the other current use-cases
- that then allows us to then completely skip some validation of the
hartid in the parser
- the biggest diff in the series is a rework of the comments in the
parser, as I have mostly found the existing (sparse) ones to not be
all that helpful whenever I have to go back and look at it
- from writing the comments, I found a conditional doing a bit of a
dance that I found counter-intuitive, so I've had a go at making that
match what I would expect a little better
- `i` implies 4 other extensions, so add them as extensions and set
them for the craic. Sure why not like...
There's a trivial numbering conflict with Evan's Zb* additions.
The other thing to consider is whether some of the extensions I am
explicitly enabling make sense in the context of ACPI. I've made sure
not to enable them where I am not sure.
Cheers,
Conor.
Changes in v3:
- Rebase on top of ACPI support & drop a patch that landed in that
series
Changes in v2:
- Pick up tags on most patches
- Drop some dt specifics from a parser comment
- Add Zicntr and Zihpm to the "always report" patch
- Note the Zicntr and Zihpm bits in the binding in a new patch.
CC: Paul Walmsley <paul.walmsley at sifive.com>
CC: Palmer Dabbelt <palmer at dabbelt.com>
CC: Conor Dooley <conor.dooley at microchip.com>
CC: Andrew Jones <ajones at ventanamicro.com>
CC: Sunil V L <sunilvl at ventanamicro.com>
CC: Yangyu Chen <cyy at cyyself.name>
CC: Rob Herring <robh+dt at kernel.org>
CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
CC: devicetree at vger.kernel.org
CC: linux-riscv at lists.infradead.org
Conor Dooley (7):
RISC-V: simplify register width check in ISA string parsing
RISC-V: split early & late of_node to hartid mapping
RISC-V: validate riscv,isa at boot, not during ISA string parsing
RISC-V: rework comments in ISA string parser
RISC-V: remove decrement/increment dance in ISA string parser
dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm
support
RISC-V: always report presence of extensions formerly part of the base
ISA
.../devicetree/bindings/riscv/cpus.yaml | 4 +-
arch/riscv/include/asm/hwcap.h | 4 +
arch/riscv/include/asm/processor.h | 1 +
arch/riscv/kernel/cpu.c | 34 +++++-
arch/riscv/kernel/cpufeature.c | 108 ++++++++++++++----
arch/riscv/kernel/smpboot.c | 2 +-
6 files changed, 123 insertions(+), 30 deletions(-)
base-commit: 748462b59f901557377b2c33ea9808ff2000e141
--
2.39.2