[PATCH v2] gpio: sifive: Add missing check for platform_get_irq

[kernel test robot]

Hi Jiasheng,

kernel test robot noticed the following build warnings:

[auto build test WARNING on brgl/gpio/for-next]
[also build test WARNING on linus/master v6.4-rc4 next-20230602]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Jiasheng-Jiang/gpio-sifive-Add-missing-check-for-platform_get_irq/20230602-152856
base:   https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git gpio/for-next
patch link:    https://lore.kernel.org/r/20230602072755.7314-1-jiasheng%40iscas.ac.cn
patch subject: [PATCH v2] gpio: sifive: Add missing check for platform_get_irq
config: openrisc-randconfig-m041-20230531 (https://download.01.org/0day-ci/archive/20230604/202306040153.RPAlkz3U-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 12.3.0

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306040153.RPAlkz3U-lkp@intel.com/

smatch warnings:
drivers/gpio/gpio-sifive.c:226 sifive_gpio_probe() warn: unsigned 'chip->irq_number[i]' is never less than zero.

vim +226 drivers/gpio/gpio-sifive.c

   179	
   180	static int sifive_gpio_probe(struct platform_device *pdev)
   181	{
   182		struct device *dev = &pdev->dev;
   183		struct device_node *node = pdev->dev.of_node;
   184		struct device_node *irq_parent;
   185		struct irq_domain *parent;
   186		struct gpio_irq_chip *girq;
   187		struct sifive_gpio *chip;
   188		int ret, ngpio, i;
   189	
   190		chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
   191		if (!chip)
   192			return -ENOMEM;
   193	
   194		chip->base = devm_platform_ioremap_resource(pdev, 0);
   195		if (IS_ERR(chip->base)) {
   196			dev_err(dev, "failed to allocate device memory\n");
   197			return PTR_ERR(chip->base);
   198		}
   199	
   200		chip->regs = devm_regmap_init_mmio(dev, chip->base,
   201						   &sifive_gpio_regmap_config);
   202		if (IS_ERR(chip->regs))
   203			return PTR_ERR(chip->regs);
   204	
   205		ngpio = of_irq_count(node);
   206		if (ngpio > SIFIVE_GPIO_MAX) {
   207			dev_err(dev, "Too many GPIO interrupts (max=%d)\n",
   208				SIFIVE_GPIO_MAX);
   209			return -ENXIO;
   210		}
   211	
   212		irq_parent = of_irq_find_parent(node);
   213		if (!irq_parent) {
   214			dev_err(dev, "no IRQ parent node\n");
   215			return -ENODEV;
   216		}
   217		parent = irq_find_host(irq_parent);
   218		of_node_put(irq_parent);
   219		if (!parent) {
   220			dev_err(dev, "no IRQ parent domain\n");
   221			return -ENODEV;
   222		}
   223	
   224		for (i = 0; i < ngpio; i++) {
   225			chip->irq_number[i] = platform_get_irq(pdev, i);
 > 226			if (chip->irq_number[i] < 0)
   227				return chip->irq_number[i];
   228		}
   229	
   230		ret = bgpio_init(&chip->gc, dev, 4,
   231				 chip->base + SIFIVE_GPIO_INPUT_VAL,
   232				 chip->base + SIFIVE_GPIO_OUTPUT_VAL,
   233				 NULL,
   234				 chip->base + SIFIVE_GPIO_OUTPUT_EN,
   235				 chip->base + SIFIVE_GPIO_INPUT_EN,
   236				 BGPIOF_READ_OUTPUT_REG_SET);
   237		if (ret) {
   238			dev_err(dev, "unable to init generic GPIO\n");
   239			return ret;
   240		}
   241	
   242		/* Disable all GPIO interrupts before enabling parent interrupts */
   243		regmap_write(chip->regs, SIFIVE_GPIO_RISE_IE, 0);
   244		regmap_write(chip->regs, SIFIVE_GPIO_FALL_IE, 0);
   245		regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IE, 0);
   246		regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
   247		chip->irq_state = 0;
   248	
   249		chip->gc.base = -1;
   250		chip->gc.ngpio = ngpio;
   251		chip->gc.label = dev_name(dev);
   252		chip->gc.parent = dev;
   253		chip->gc.owner = THIS_MODULE;
   254		girq = &chip->gc.irq;
   255		gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
   256		girq->fwnode = of_node_to_fwnode(node);
   257		girq->parent_domain = parent;
   258		girq->child_to_parent_hwirq = sifive_gpio_child_to_parent_hwirq;
   259		girq->handler = handle_bad_irq;
   260		girq->default_type = IRQ_TYPE_NONE;
   261	
   262		platform_set_drvdata(pdev, chip);
   263		return gpiochip_add_data(&chip->gc, chip);
   264	}
   265	

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