[PATCH v2 2/3] dt-bindings: iio: adc: Add Allwinner D1/T113s/R329/T507 SoCs GPADC
Maksim Kiselev
bigunclemax at gmail.com
Thu Jun 1 15:30:40 PDT 2023
From: Maxim Kiselev <bigunclemax at gmail.com>
Allwinner's D1/T113s/R329/T507 SoCs have a new general purpose ADC.
This ADC is the same for all of this SoCs. The only difference is
the number of available channels.
Signed-off-by: Maxim Kiselev <bigunclemax at gmail.com>
---
.../iio/adc/allwinner,sun20i-d1-gpadc.yaml | 79 +++++++++++++++++++
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml
diff --git a/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml
new file mode 100644
index 000000000000..94f15bb48231
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/allwinner,sun20i-d1-gpadc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner D1 General Purpose ADC
+
+properties:
+ "#io-channel-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ compatible:
+ enum:
+ - allwinner,sun20i-d1-gpadc
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - "#io-channel-cells"
+ - clocks
+ - compatible
+ - interrupts
+ - reg
+ - resets
+
+patternProperties:
+ "^channel@([0-15])$":
+ $ref: adc.yaml
+ type: object
+ description: |
+ Represents the internal channels of the ADC.
+
+ properties:
+ reg:
+ description: |
+ The channel number.
+ Up to 16 channels, numbered from 0 to 15.
+ items:
+ minimum: 0
+ maximum: 15
+
+ required:
+ - reg
+
+ additionalProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ gpadc: adc at 2009000 {
+ compatible = "allwinner,sun20i-d1-gpadc";
+ reg = <0x2009000 0x1000>;
+ clocks = <&ccu 80>;
+ resets = <&ccu 32>;
+ interrupts = <0 57 4>;
+ #io-channel-cells = <1>;
+
+ channel at 0 {
+ reg = <0>;
+ };
+
+ channel at 1 {
+ reg = <1>;
+ };
+ };
+
+...
--
2.39.2
More information about the linux-riscv
mailing list