[v2, 3/5] riscv: Add vector extension XOR implementation

[Conor Dooley]

On Fri, Jul 21, 2023 at 11:28:53AM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu at sifive.com>
> 
> This patch adds support for vector optimized XOR and it is tested in
> qemu.
> 
> Co-developed-by: Han-Kuan Chen <hankuan.chen at sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen at sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>

Other than the inherited build failure from 2/5, this seems okay to me.
I have no opinion on the asm bits, so
Acked-by: Conor Dooley <conor.dooley at microchip.com>

Thanks,
Conor.
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