[v1, 3/6] riscv: Add vector extension XOR implementation

Conor Dooley conor.dooley at microchip.com
Mon Jul 17 03:25:34 PDT 2023


On Sat, Jul 15, 2023 at 03:00:29PM +0000, Andy Chiu wrote:
> From: Greentime Hu <greentime.hu at sifive.com>
> 
> This patch adds support for vector optimized XOR and it is tested in
> qemu.

Since this patch was originally written, has it been tested in hardware?

> Co-developed-by: Han-Kuan Chen <hankuan.chen at sifive.com>
> Signed-off-by: Han-Kuan Chen <hankuan.chen at sifive.com>
> Signed-off-by: Greentime Hu <greentime.hu at sifive.com>
> Signed-off-by: Andy Chiu <andy.chiu at sifive.com>
> ---
>  arch/riscv/include/asm/xor.h | 82 ++++++++++++++++++++++++++++++++++++
>  arch/riscv/lib/Makefile      |  1 +
>  arch/riscv/lib/xor.S         | 81 +++++++++++++++++++++++++++++++++++
>  3 files changed, 164 insertions(+)
>  create mode 100644 arch/riscv/include/asm/xor.h
>  create mode 100644 arch/riscv/lib/xor.S
> 
> diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h
> new file mode 100644
> index 000000000000..81b8837fa161
> --- /dev/null
> +++ b/arch/riscv/include/asm/xor.h

> +static void xor_rvv_2(unsigned long bytes, unsigned long *__restrict p1,
> +		      const unsigned long *__restrict p2)

> +static void xor_rvv_3(unsigned long bytes, unsigned long *__restrict p1,
> +		      const unsigned long *__restrict p2,
> +		      const unsigned long *__restrict p3)

> +static void xor_rvv_4(unsigned long bytes, unsigned long *__restrict p1,
> +		      const unsigned long *__restrict p2,
> +		      const unsigned long *__restrict p3,
> +		      const unsigned long *__restrict p4)

> +
> +static void xor_rvv_5(unsigned long bytes, unsigned long *__restrict p1,
> +		      const unsigned long *__restrict p2,
> +		      const unsigned long *__restrict p3,
> +		      const unsigned long *__restrict p4,
> +		      const unsigned long *__restrict p5)

> +
> +static struct xor_block_template xor_block_rvv = {
> +	.name = "rvv",
> +	.do_2 = xor_rvv_2,
> +	.do_3 = xor_rvv_3,
> +	.do_4 = xor_rvv_4,
> +	.do_5 = xor_rvv_5
> +};

Same naming scheme comments as the main vector patchset and 2/6 apply
here too.
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