[v1, 0/6] riscv: support kernel-mode Vector

Heiko Stuebner heiko at sntech.de
Sun Jul 16 02:26:03 PDT 2023


Am Samstag, 15. Juli 2023, 17:00:26 CEST schrieb Andy Chiu:
> This series provides support for running Vector code in kernel mode. The
> implementation is based on the v12 series of the Vector series, but with
> some additions. First, we introduce a mechanism to defer restoring
> Vector context for userspace programs (patch 1). This is similar to
> arm64 and x86's approaches when dealing with extra userspace register
> context. And it is benefitial to both Vector in user and kernel-mode.
> Then, patch 2, 3 add the kernel-mode Vector patch from v12 with minor
> modifications. At the end of the series, patch 4, 5, 6 add supports for
> making kernel-mode Vector code preemptible. We do this by adding
> kernel-mode Vector context, and keeping track of the frame where V
> context is last valid. We believe that enabling preemption of running V
> is a critical path for getting V more generally available in the
> kernel-mode. Besides, with status.VS, we can easily tell if
> saving/restoring V is required. This reduce the level of cost when
> running SIMD in kernel mode as compared to other arches. Other arches
> usually do not have a way to tell if extra context is dirty. Thus, if
> they also want to support running preemptible code with extra registers,
> then they must save/restore extra context at each context switch even if
> registers are not dirty.
> 
> The series is tested by loading a kernel module on a preemptive kernel.
> The module launches multiple kworkers which run Vector operations and
> verifies with scalar code. Also, the module provides userspace intefaces
> via fops to verify if we can run Vector code on syscall path.
> 
> Changes from the vector v12 series (for patch 2, 3):
>  - return a failure code when kernel_rvv_begin() fails.
>  - Do not immediately restore user's V context.

This works nicely with my vector crypto patchset rebased on
top of it:

Tested-by: Heiko Stuebner <heiko at sntech.de>





More information about the linux-riscv mailing list