[PATCH] RISC-V: Provide a more helpful error message on invalid ISA strings
Palmer Dabbelt
palmer at rivosinc.com
Thu Jul 6 10:28:21 PDT 2023
On Thu, 29 Jun 2023 16:17:27 PDT (-0700), Conor Dooley wrote:
> Yo,
>
> On Thu, Jun 29, 2023 at 03:35:03PM -0700, Palmer Dabbelt wrote:
>> Right now we provide a somewhat unhelpful error message on systems with
>> invalid error messages, something along the lines of
>>
>> [ 0.000000] CPU with hartid=0 is not available
>> [ 0.000000] ------------[ cut here ]------------
>> [ 0.000000] kernel BUG at arch/riscv/kernel/smpboot.c:174!
>> [ 0.000000] Kernel BUG [#1]
>> [ 0.000000] Modules linked in:
>> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 6.4.0-rc1-00096-ge0097d2c62d5-dirty #1
>> [ 0.000000] Hardware name: Microchip PolarFire-SoC Icicle Kit (DT)
>> [ 0.000000] epc : of_parse_and_init_cpus+0x16c/0x16e
>> [ 0.000000] ra : of_parse_and_init_cpus+0x9a/0x16e
>> [ 0.000000] epc : ffffffff80c04e0a ra : ffffffff80c04d38 sp : ffffffff81603e20
>> [ 0.000000] gp : ffffffff8182d658 tp : ffffffff81613f80 t0 : 000000000000006e
>> [ 0.000000] t1 : 0000000000000064 t2 : 0000000000000000 s0 : ffffffff81603e80
>> [ 0.000000] s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000
>> [ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000
>> [ 0.000000] a5 : 0000000000001fff a6 : 0000000000001fff a7 : ffffffff816148b0
>> [ 0.000000] s2 : 0000000000000001 s3 : ffffffff81492a4c s4 : ffffffff81a4b090
>> [ 0.000000] s5 : ffffffff81506030 s6 : 0000000000000040 s7 : 0000000000000000
>> [ 0.000000] s8 : 00000000bfb6f046 s9 : 0000000000000001 s10: 0000000000000000
>> [ 0.000000] s11: 00000000bf389700 t3 : 0000000000000000 t4 : 0000000000000000
>> [ 0.000000] t5 : ffffffff824dd188 t6 : ffffffff824dd187
>> [ 0.000000] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003
>> [ 0.000000] [<ffffffff80c04e0a>] of_parse_and_init_cpus+0x16c/0x16e
>> [ 0.000000] [<ffffffff80c04c96>] setup_smp+0x1e/0x26
>> [ 0.000000] [<ffffffff80c03ffe>] setup_arch+0x6e/0xb2
>> [ 0.000000] [<ffffffff80c00384>] start_kernel+0x72/0x400
>> [ 0.000000] Code: 80e7 4a00 a603 0009 b795 1097 ffe5 80e7 92c0 9002 (9002) 715d
>> [ 0.000000] ---[ end trace 0000000000000000 ]---
>> [ 0.000000] Kernel panic - not syncing: Fatal exception in interrupt
>>
>> This adds a warning for the cases where the ISA string isn't valid. It's still
>> above the BUG_ON cut, but hopefully it's at least a bit easier for users.
>>
>> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
>> ---
>> I haven't tried this yet, but Conor posted the log as we were discussing
>> the DT deprecation at
>> <https://lore.kernel.org/all/20230629-angled-gallantly-8fe7451a25fa@spud/>.
>
> If you are gonna apply this for v6.5:
> Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
> Otherwise, can I take this in my series? I probably need to extend it a la:
I forgot about it and it looks like Drew pointed out some small issue.
Do you want to just clean that up and pick it up with your series?
> [ 0.000000] CPU with hartid=0 is not available
> [ 0.000000] CPU with hartid=1 is invalid, this kernel does not parse riscv,isa
> [ 0.000000] CPU with hartid=2 is invalid, this kernel does not parse riscv,isa
> [ 0.000000] CPU with hartid=3 is invalid, this kernel does not parse riscv,isa
> [ 0.000000] CPU with hartid=4 is invalid, this kernel does not parse riscv,isa
> [ 0.000000] ------------[ cut here ]------------
> [ 0.000000] kernel BUG at arch/riscv/kernel/smpboot.c:174!
> [ 0.000000] Kernel BUG [#1]
> [ 0.000000] Modules linked in:
> [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 6.4.0-rc1-00098-g372a21066d8a-dirty #1
> [ 0.000000] Hardware name: Microchip PolarFire-SoC Icicle Kit (DT)
> [ 0.000000] epc : of_parse_and_init_cpus+0x1de/0x1e0
> [ 0.000000] ra : of_parse_and_init_cpus+0xae/0x1e0
> [ 0.000000] epc : ffffffff80c0580c ra : ffffffff80c056dc sp : ffffffff81603dc0
> [ 0.000000] gp : ffffffff818a9538 tp : ffffffff81614680 t0 : 000000000000006e
> [ 0.000000] t1 : 0000000000000064 t2 : 0000000000000000 s0 : ffffffff81603e40
> [ 0.000000] s1 : 0000000000000000 a0 : 0000000000000000 a1 : 0000000000000000
> [ 0.000000] a2 : ffffffff818b01f8 a3 : 0000000000000000 a4 : 0000000000000000
> [ 0.000000] a5 : 0000000000001fff a6 : 0000000000001fff a7 : ffffffff808fc878
> [ 0.000000] s2 : 0000000000000001 s3 : ffffffff813675bc s4 : ffffffff81617520
> [ 0.000000] s5 : 00000000bfbe35c0 s6 : ffffffff818b0090 s7 : ffffffff813e1cf0
> [ 0.000000] s8 : 0000000000000040 s9 : 0000000000000000 s10: 0000000000000000
> [ 0.000000] s11: 00000000bf389700 t3 : 0000000000000000 t4 : 0000000000000000
> [ 0.000000] t5 : ffffffff82342188 t6 : ffffffff82342187
> [ 0.000000] status: 0000000200000100 badaddr: 0000000000000000 cause: 0000000000000003
> [ 0.000000] [<ffffffff80c0580c>] of_parse_and_init_cpus+0x1de/0x1e0
> [ 0.000000] [<ffffffff80c05626>] setup_smp+0x1e/0x26
> [ 0.000000] [<ffffffff80c045fa>] setup_arch+0x6e/0xb2
> [ 0.000000] [<ffffffff80c0036a>] start_kernel+0x80/0x81a
> [ 0.000000] Code: fe75 85ca a0ef 98b2 a603 000a bf19 00ef 97a3 9002 (9002) 7159
> [ 0.000000] ---[ end trace 0000000000000000 ]---
> [ 0.000000] Kernel panic - not syncing: Fatal exception in interrupt
>
> with something like:
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 99df12262a3e..708ff4757413 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -64,25 +64,34 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har
> if (of_property_read_string(node, "riscv,isa-base", &isa))
> goto old_interface;
>
> - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5))
> + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {
> + pr_warn("CPU with hartid=%lu does not support rv32i", *hart);
> return -ENODEV;
> + }
>
> - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5))
> + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {
> + pr_warn("CPU with hartid=%lu does not support rv64i", *hart);
> return -ENODEV;
> + }
>
> if (!of_property_present(node, "riscv,isa-extensions"))
> return -ENODEV;
>
> if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||
> of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||
> - of_property_match_string(node, "riscv,isa-extensions", "a") < 0)
> + of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {
> + pr_warn("CPU with hartid=%lu does not support ima", *hart);
> return -ENODEV;
> + }
>
> return 0;
>
> old_interface:
> - if (!IS_ENABLED(CONFIG_RISCV_ISA_FALLBACK) && !riscv_isa_fallback_cmdline)
> + if (!IS_ENABLED(CONFIG_RISCV_ISA_FALLBACK) && !riscv_isa_fallback_cmdline) {
> + pr_warn("CPU with hartid=%lu is invalid, this kernel does not parse riscv,isa",
> + *hart);
> return -ENODEV;
> + }
>
> if (of_property_read_string(node, "riscv,isa", &isa)) {
> pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",
>
>
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