[PATCH -next v5 1/2] riscv: kdump: Implement crashkernel=X,[high,low]

chenjiahao (C) chenjiahao16 at huawei.com
Mon Jul 3 20:51:08 PDT 2023


On 2023/7/2 12:06, Baoquan He wrote:
> On 07/01/23 at 05:51pm, chenjiahao (C) wrote:
> ......
>> I have sent v6 patches, implementing the logic above. That fixes the
>> retrying
>>
>> logic and should be aligned with Arm64 code.
> Hmm, it has improved much, while there's still issue which need be
> fixed. You missed the case that crsahkernel low is specified as zero
> explicitly. Obviously your v6 is not able to handle that well. Means
> your v6 is not aligned with the current arm64 code completely.
>
> crashkernel=xM,high crashkernel=0M,low
>
>>
>> Please let me know if there is any problem remains.
> Earlier, I posted below RFC patchset to try to unify the
> crashkernel=,high support on x86, arm64 and risc-v, the generic arch.
> Wondering what you think about it. risc-v can be added in with very few
> change to get the crahskernel=,high support.
>
> [RFC PATCH 0/4] kdump: add generic functions to simplify crashkernel crashkernel in architecture
>
> Surely, the crashkernel=,high support can be added independently in
> advance. Later my patchset can unify them and remove the duplicated code
> in risc-v. It's up to you and risc-v maintainers/reivewers to take one.
> Anyway, I will add comment to your v6 to point out the issue.

It would be great if crashkernel parsing and reserving logic could be
unified on multiple architectures, the code would be more straightforward
and easy to use. I will have a more in-depth review of your RFC patchset
later.

Meanwhile, I will continue to update my patchset on risc-v, just wishing
to complement this feature earlier. When your unify solution get applied,
simply remove the duplicate part is OK. Before that, I will update my
risc-v code and further align with the Arm64 logic.

Thanks for your carefully review, I will fix the issue above and send
v7 patchset soon.

Thanks,
Jiahao

>
> Thanks
> Baoquan
>



More information about the linux-riscv mailing list