[PATCH v3 4/7] dt-bindings: Add RISC-V misaligned access performance

[Conor Dooley]

Hey Evan,

On Tue, Feb 21, 2023 at 11:08:55AM -0800, Evan Green wrote:
> From: Palmer Dabbelt <palmer at rivosinc.com>
> 
> This key allows device trees to specify the performance of misaligned
> accesses to main memory regions from each CPU in the system.

Could you fold some of Palmer's explanation for why this must be in the
devicetree? Think this is where he explained it:
https://lore.kernel.org/all/mhng-8736b349-e27a-4372-81ca-3a25d2ec1e94@palmer-ri-x1c9/

> 
> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> Signed-off-by: Evan Green <evan at rivosinc.com>
> ---
> 
> Changes in v3:
>  - Added | to description: to make dt-checker happy.
> 
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index c6720764e765..f79e9e5c5ee9 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -85,6 +85,21 @@ properties:
>      $ref: "/schemas/types.yaml#/definitions/string"
>      pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$
>  
> +  riscv,misaligned-access-performance:
> +    description: |
> +      Identifies the performance of misaligned memory accesses to main memory
> +      regions.  There are three flavors of unaligned access performance: "emulated"
> +      means that misaligned accesses are emulated via software and thus
> +      extremely slow, "slow" means that misaligned accesses are supported by
> +      hardware but still slower that aligned accesses sequences, and "fast"

s/that/than/

> +      means that misaligned accesses are as fast or faster than the
> +      cooresponding aligned accesses sequences.

s/cooresponding/corresponding/

Thanks,
Conor.

> +    $ref: "/schemas/types.yaml#/definitions/string"
> +    enum:
> +      - emulated
> +      - slow
> +      - fast
> +
>    # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here
>    timebase-frequency: false
>  
> -- 
> 2.25.1
> 
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