[PATCH V2] clocksource: riscv: Patch riscv_clock_next_event() jump before first use
Anup Patel
anup at brainfault.org
Wed Feb 1 20:09:14 PST 2023
On Thu, Feb 2, 2023 at 1:19 AM Matt Evans <mev at rivosinc.com> wrote:
>
> A static key is used to select between SBI and Sstc timer usage in
> riscv_clock_next_event(), but currently the direction is resolved
> after cpuhp_setup_state() is called (which sets the next event). The
> first event will therefore fall through the sbi_set_timer() path; this
> breaks Sstc-only systems. So, apply the jump patching before first
> use.
>
> Fixes: 9f7a8ff6391f ("RISC-V: Prefer sstc extension if available")
> Signed-off-by: Matt Evans <mev at rivosinc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup at brainfault.org>
Regards,
Anup
> ---
>
> V1 -> V2: Commit msg tweak.
>
> drivers/clocksource/timer-riscv.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index 969a552da8d2..a36d173fd6cd 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -177,6 +177,11 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> return error;
> }
>
> + if (riscv_isa_extension_available(NULL, SSTC)) {
> + pr_info("Timer interrupt in S-mode is available via sstc extension\n");
> + static_branch_enable(&riscv_sstc_available);
> + }
> +
> error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
> "clockevents/riscv/timer:starting",
> riscv_timer_starting_cpu, riscv_timer_dying_cpu);
> @@ -184,11 +189,6 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> pr_err("cpu hp setup state failed for RISCV timer [%d]\n",
> error);
>
> - if (riscv_isa_extension_available(NULL, SSTC)) {
> - pr_info("Timer interrupt in S-mode is available via sstc extension\n");
> - static_branch_enable(&riscv_sstc_available);
> - }
> -
> return error;
> }
>
> --
> 2.30.2
>
>
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