[PATCH v3 00/12] RISC-V: provide some accelerated cryptography implementations using vector extensions

[Eric Biggers]

Hi Jerry,

On Thu, Dec 21, 2023 at 11:48:27PM -0600, Eric Biggers wrote:
> Hi Jerry,
> 
> On Tue, Dec 05, 2023 at 05:27:49PM +0800, Jerry Shih wrote:
> > Changelog v2:
> >  - Turn to use simd skcipher interface for AES-CBC/CTR/ECB/XTS and
> >    Chacha20.
> 
> If I understand correctly, the RISC-V kernel-mode vector support now seems to be
> heading down the path of supporting softirq context, as I had suggested
> originally.  With patches 1-2 of Andy Chiu's latest patchset
> "[v7, 00/10] riscv: support kernel-mode Vector"
> (https://lore.kernel.org/linux-riscv/20231221134318.28105-1-andy.chiu@sifive.com).
> applied, the kernel has basic support for kernel-mode vector, including in
> softirq context.
> 
> With that being the case, "skcipher" algorithms can just use the RISC-V vector
> unit unconditionally, given that skcipher only supports task and softirq
> context.  Therefore, can you consider undoing your change that added fallbacks
> using the simd helper (crypto/simd.c)?  Thanks!
> 

I had a go at incorporating my suggestions into your patchset, and rebasing the
patchset onto riscv/for-next plus the first two patches of "[v9, 00/10] riscv:
support kernel-mode Vector".  You can get the result from branch "riscv-crypto"
of https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git.
Everything seems to work (tested in QEMU, as usual).

Please consider using it when you send out v4; thanks!  I can even send it out
myself, if you want, but I assume you're still "owning" the patchset.

- Eric