[PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation

[Conor Dooley]

On Wed, Dec 27, 2023 at 09:57:38AM -0800, Samuel Holland wrote:
> The current description implies that only a single address translation
> mode is available to the operating system. However, some implementations
> support multiple address translation modes, and the operating system is
> free to choose between them.
> 
> Per the RISC-V privileged specification, Sv48 implementations must also
> implement Sv39, and likewise Sv57 implies support for Sv48. This means
> it is possible to describe all supported address translation modes using
> a single value, by naming the largest supported mode. This appears to
> have been the intended usage of the property, so note it explicitly.
> 
> Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
> Signed-off-by: Samuel Holland <samuel.holland at sifive.com>

Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

Cheers,
Conor.


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