[PATCH v6 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042
Yu Chien Peter Lin
peterlin at andestech.com
Mon Dec 25 02:33:05 PST 2023
xtheadpmu stands for T-Head Performance Monitor Unit extension.
Based on the added T-Head PMU ISA string, the SBI PMU driver
will make use of the non-standard irq source.
Signed-off-by: Yu Chien Peter Lin <peterlin at andestech.com>
Acked-by: Conor Dooley <conor.dooley at microchip.com>
---
Changes v4 -> v5:
- New patch
Changes v5 -> v6:
- Include Conor's Acked-by
---
arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
1 file changed, 64 insertions(+), 64 deletions(-)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index b136b6c4128c..1d0b236f2e7a 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -260,7 +260,7 @@ cpu0: cpu at 0 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -285,7 +285,7 @@ cpu1: cpu at 1 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -310,7 +310,7 @@ cpu2: cpu at 2 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -335,7 +335,7 @@ cpu3: cpu at 3 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -360,7 +360,7 @@ cpu4: cpu at 4 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <4>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -385,7 +385,7 @@ cpu5: cpu at 5 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <5>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -410,7 +410,7 @@ cpu6: cpu at 6 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <6>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -435,7 +435,7 @@ cpu7: cpu at 7 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <7>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -460,7 +460,7 @@ cpu8: cpu at 8 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <8>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -485,7 +485,7 @@ cpu9: cpu at 9 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <9>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -510,7 +510,7 @@ cpu10: cpu at 10 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <10>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -535,7 +535,7 @@ cpu11: cpu at 11 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <11>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -560,7 +560,7 @@ cpu12: cpu at 12 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <12>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -585,7 +585,7 @@ cpu13: cpu at 13 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <13>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -610,7 +610,7 @@ cpu14: cpu at 14 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <14>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -635,7 +635,7 @@ cpu15: cpu at 15 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <15>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -660,7 +660,7 @@ cpu16: cpu at 16 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <16>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -685,7 +685,7 @@ cpu17: cpu at 17 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <17>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -710,7 +710,7 @@ cpu18: cpu at 18 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <18>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -735,7 +735,7 @@ cpu19: cpu at 19 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <19>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -760,7 +760,7 @@ cpu20: cpu at 20 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <20>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -785,7 +785,7 @@ cpu21: cpu at 21 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <21>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -810,7 +810,7 @@ cpu22: cpu at 22 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <22>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -835,7 +835,7 @@ cpu23: cpu at 23 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <23>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -860,7 +860,7 @@ cpu24: cpu at 24 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <24>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -885,7 +885,7 @@ cpu25: cpu at 25 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <25>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -910,7 +910,7 @@ cpu26: cpu at 26 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <26>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -935,7 +935,7 @@ cpu27: cpu at 27 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <27>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -960,7 +960,7 @@ cpu28: cpu at 28 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <28>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -985,7 +985,7 @@ cpu29: cpu at 29 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <29>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1010,7 +1010,7 @@ cpu30: cpu at 30 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <30>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1035,7 +1035,7 @@ cpu31: cpu at 31 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <31>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1060,7 +1060,7 @@ cpu32: cpu at 32 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <32>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1085,7 +1085,7 @@ cpu33: cpu at 33 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <33>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1110,7 +1110,7 @@ cpu34: cpu at 34 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <34>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1135,7 +1135,7 @@ cpu35: cpu at 35 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <35>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1160,7 +1160,7 @@ cpu36: cpu at 36 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <36>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1185,7 +1185,7 @@ cpu37: cpu at 37 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <37>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1210,7 +1210,7 @@ cpu38: cpu at 38 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <38>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1235,7 +1235,7 @@ cpu39: cpu at 39 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <39>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1260,7 +1260,7 @@ cpu40: cpu at 40 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <40>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1285,7 +1285,7 @@ cpu41: cpu at 41 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <41>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1310,7 +1310,7 @@ cpu42: cpu at 42 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <42>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1335,7 +1335,7 @@ cpu43: cpu at 43 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <43>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1360,7 +1360,7 @@ cpu44: cpu at 44 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <44>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1385,7 +1385,7 @@ cpu45: cpu at 45 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <45>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1410,7 +1410,7 @@ cpu46: cpu at 46 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <46>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1435,7 +1435,7 @@ cpu47: cpu at 47 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <47>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1460,7 +1460,7 @@ cpu48: cpu at 48 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <48>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1485,7 +1485,7 @@ cpu49: cpu at 49 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <49>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1510,7 +1510,7 @@ cpu50: cpu at 50 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <50>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1535,7 +1535,7 @@ cpu51: cpu at 51 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <51>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1560,7 +1560,7 @@ cpu52: cpu at 52 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <52>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1585,7 +1585,7 @@ cpu53: cpu at 53 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <53>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1610,7 +1610,7 @@ cpu54: cpu at 54 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <54>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1635,7 +1635,7 @@ cpu55: cpu at 55 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <55>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1660,7 +1660,7 @@ cpu56: cpu at 56 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <56>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1685,7 +1685,7 @@ cpu57: cpu at 57 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <57>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1710,7 +1710,7 @@ cpu58: cpu at 58 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <58>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1735,7 +1735,7 @@ cpu59: cpu at 59 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <59>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1760,7 +1760,7 @@ cpu60: cpu at 60 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <60>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1785,7 +1785,7 @@ cpu61: cpu at 61 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <61>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1810,7 +1810,7 @@ cpu62: cpu at 62 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <62>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -1835,7 +1835,7 @@ cpu63: cpu at 63 {
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
"zicntr", "zicsr", "zifencei",
- "zihpm";
+ "zihpm", "xtheadpmu";
reg = <63>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
--
2.34.1
More information about the linux-riscv
mailing list