[PATCH v10 3/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration
Emil Renner Berthing
emil.renner.berthing at canonical.com
Sun Dec 24 02:49:34 PST 2023
William Qiu wrote:
> Add OpenCores PWM controller node and add PWM pins configuration
> on VisionFive 1 board.
>
> Signed-off-by: William Qiu <william.qiu at starfivetech.com>
Sorry, I thought I already sent my review. This looks good.
Reviewed-by: Emil Renner Berthing <emil.renner.berthing at canonical.com>
> ---
> .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> index b93ce351a90f..11876906cc05 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi
> @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN,
> };
> };
>
> + pwm_pins: pwm-0 {
> + pwm-pins {
> + pinmux = <GPIOMUX(7,
> + GPO_PWM_PAD_OUT_BIT0,
> + GPO_PWM_PAD_OE_N_BIT0,
> + GPI_NONE)>,
> + <GPIOMUX(5,
> + GPO_PWM_PAD_OUT_BIT1,
> + GPO_PWM_PAD_OE_N_BIT1,
> + GPI_NONE)>;
> + bias-disable;
> + drive-strength = <35>;
> + input-disable;
> + input-schmitt-disable;
> + slew-rate = <0>;
> + };
> + };
> +
> uart3_pins: uart3-0 {
> rx-pins {
> pinmux = <GPIOMUX(13, GPO_LOW, GPO_DISABLE,
> @@ -154,6 +172,12 @@ &osc_aud {
> clock-frequency = <27000000>;
> };
>
> +&pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm_pins>;
> + status = "okay";
> +};
> +
> &uart3 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart3_pins>;
> diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> index e68cafe7545f..4f5eb2f60856 100644
> --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
> @@ -280,6 +280,15 @@ watchdog at 12480000 {
> <&rstgen JH7100_RSTN_WDT>;
> };
>
> + pwm: pwm at 12490000 {
> + compatible = "starfive,jh7100-pwm", "opencores,pwm-v1";
> + reg = <0x0 0x12490000 0x0 0x10000>;
> + clocks = <&clkgen JH7100_CLK_PWM_APB>;
> + resets = <&rstgen JH7100_RSTN_PWM_APB>;
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> sfctemp: temperature-sensor at 124a0000 {
> compatible = "starfive,jh7100-temp";
> reg = <0x0 0x124a0000 0x0 0x10000>;
> --
> 2.34.1
>
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