[PATCH 1/1] riscv: set ARCH_DMA_DEFAULT_COHERENT if RISCV_DMA_NONCOHERENT is not set

[Christoph Hellwig]

On Thu, Dec 21, 2023 at 10:27:33PM +0000, Jiaxun Yang wrote:
>
>
> 在 2023/12/21 20:29, Conor Dooley 写道:
>> + Christoph
>>
>> I don't think this patch is correct. Regardless of whether we support
>> cache management operations, DMA is assumed to be coherent unless
>> peripherals etc are specified to otherwise in DT (or however ACPI deals
>> with that kind of thing).
>>
>> What problem are you trying to solve here?
>>
>> On Thu, Dec 21, 2023 at 09:51:52PM +0300, Maxim Kochetkov wrote:
>>> Not all the RISCV are DMA coherent by default.
>
> Sorry for chime in here.
> IMO if your platform is not coherent by default, just insert 
> "dma-noncoherent"
> at devicetree root node.

Exactly.  ARCH_DMA_DEFAULT_COHERENTis a setting that just says for
a given architecture assumes coherent unless otherwise specified,
which has historically been the case for mips.  Not setting it means
non-coherent unless specified, which has historially been the case
for arm.

RISC-V starte out without support for non-coherent DMA, and high ups
in RISCV still told me in 2019 that RISC-V doesn't need cache
management instructions because no new hardware would ever not be
dma coherent.  Yeah, right..

Anyay, Linux for RISC-V has historically been coherent only and then
coherent default, so this option is wrong, and you need to mark
you platform as non-coherent by inserting dma-noncoherent somewhere.