[PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver

[JeeHeng Sia]

> -----Original Message-----
> From: Emil Renner Berthing <emil.renner.berthing at canonical.com>
> Sent: Wednesday, December 20, 2023 9:08 PM
> To: JeeHeng Sia <jeeheng.sia at starfivetech.com>; Emil Renner Berthing <emil.renner.berthing at canonical.com>; kernel at esmil.dk;
> conor at kernel.org; robh+dt at kernel.org; krzysztof.kozlowski+dt at linaro.org; paul.walmsley at sifive.com; palmer at dabbelt.com;
> aou at eecs.berkeley.edu; mturquette at baylibre.com; sboyd at kernel.org; p.zabel at pengutronix.de; Hal Feng
> <hal.feng at starfivetech.com>; Xingyu Wu <xingyu.wu at starfivetech.com>
> Cc: linux-riscv at lists.infradead.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-clk at vger.kernel.org; Leyfoon Tan
> <leyfoon.tan at starfivetech.com>
> Subject: RE: [PATCH v1 06/16] clk: starfive: Add JH8100 System clock generator driver
> 
> JeeHeng Sia wrote:
[...]
> > >
> > > If you're just using this for testing on FPGAs you can create dummy fixed
> > > clocks in the device tree for the PLLs that this driver can consume.  Then
> > > later when you have a PLL driver you can replace those fixed clocks with the
> > > output of that driver.
> > The PLL fixed clocks were created in the C code. I interpret this message
> > as a suggestion to create a PLL fixed clock in the DT?
> 
> Yes, then you don't need to change the clock driver and its bindings but just
> need to update the clock references to the PLL driver once you have that.
Ok.
> 
> /Emil