[PATCH v2 13/13] RISC-V: KVM: selftests: Add get-reg-list test for STA registers

[Anup Patel]

On Thu, Dec 14, 2023 at 3:46 PM Andrew Jones <ajones at ventanamicro.com> wrote:
>
> Add SBI STA and its two registers to the get-reg-list test.
>
> Signed-off-by: Andrew Jones <ajones at ventanamicro.com>

LGTM.

Reviewed-by: Anup Patel <anup at brainfault.org>

Regards,
Anup

> ---
>  .../selftests/kvm/riscv/get-reg-list.c        | 43 +++++++++++++++++++
>  1 file changed, 43 insertions(+)
>
> diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> index b8da2e86bf9c..55dd1fc3c536 100644
> --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
> +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
> @@ -71,6 +71,7 @@ bool filter_reg(__u64 reg)
>         case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_HSM:
>         case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU:
>         case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN:
> +       case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA:
>         case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL:
>         case KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR:
>                 return true;
> @@ -461,6 +462,7 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_off)
>                 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_SRST),
>                 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_HSM),
>                 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU),
> +               KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_STA),
>                 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL),
>                 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR),
>                 KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN),
> @@ -509,6 +511,32 @@ static const char *sbi_ext_id_to_str(const char *prefix, __u64 id)
>         return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
>  }
>
> +static const char *sbi_sta_id_to_str(__u64 reg_off)
> +{
> +       switch (reg_off) {
> +       case 0: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo)";
> +       case 1: return "KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi)";
> +       }
> +       return strdup_printf("KVM_REG_RISCV_SBI_STA | %lld /* UNKNOWN */", reg_off);
> +}
> +
> +static const char *sbi_id_to_str(const char *prefix, __u64 id)
> +{
> +       __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_SBI);
> +       __u64 reg_subtype = reg_off & KVM_REG_RISCV_SUBTYPE_MASK;
> +
> +       assert((id & KVM_REG_RISCV_TYPE_MASK) == KVM_REG_RISCV_SBI);
> +
> +       reg_off &= ~KVM_REG_RISCV_SUBTYPE_MASK;
> +
> +       switch (reg_subtype) {
> +       case KVM_REG_RISCV_SBI_STA:
> +               return sbi_sta_id_to_str(reg_off);
> +       }
> +
> +       return strdup_printf("%lld | %lld /* UNKNOWN */", reg_subtype, reg_off);
> +}
> +
>  void print_reg(const char *prefix, __u64 id)
>  {
>         const char *reg_size = NULL;
> @@ -565,6 +593,10 @@ void print_reg(const char *prefix, __u64 id)
>                 printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI_EXT | %s,\n",
>                                 reg_size, sbi_ext_id_to_str(prefix, id));
>                 break;
> +       case KVM_REG_RISCV_SBI:
> +               printf("\tKVM_REG_RISCV | %s | KVM_REG_RISCV_SBI | %s,\n",
> +                               reg_size, sbi_id_to_str(prefix, id));
> +               break;
>         default:
>                 printf("\tKVM_REG_RISCV | %s | 0x%llx /* UNKNOWN */,\n",
>                                 reg_size, id & ~REG_MASK);
> @@ -651,6 +683,12 @@ static __u64 sbi_base_regs[] = {
>         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR,
>  };
>
> +static __u64 sbi_sta_regs[] = {
> +       KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_STA,
> +       KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_lo),
> +       KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI | KVM_REG_RISCV_SBI_STA | KVM_REG_RISCV_SBI_STA_REG(shmem_hi),
> +};
> +
>  static __u64 zicbom_regs[] = {
>         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CONFIG | KVM_REG_RISCV_CONFIG_REG(zicbom_block_size),
>         KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZICBOM,
> @@ -757,6 +795,9 @@ static __u64 fp_d_regs[] = {
>  #define SUBLIST_SBI_BASE \
>         {"sbi-base", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_V01, \
>          .regs = sbi_base_regs, .regs_n = ARRAY_SIZE(sbi_base_regs),}
> +#define SUBLIST_SBI_STA \
> +       {"sbi-sta", .feature_type = VCPU_FEATURE_SBI_EXT, .feature = KVM_RISCV_SBI_EXT_STA, \
> +        .regs = sbi_sta_regs, .regs_n = ARRAY_SIZE(sbi_sta_regs),}
>  #define SUBLIST_ZICBOM \
>         {"zicbom", .feature = KVM_RISCV_ISA_EXT_ZICBOM, .regs = zicbom_regs, .regs_n = ARRAY_SIZE(zicbom_regs),}
>  #define SUBLIST_ZICBOZ \
> @@ -832,6 +873,7 @@ static struct vcpu_reg_list config_sbi_##ext = {            \
>  /* Note: The below list is alphabetically sorted. */
>
>  KVM_SBI_EXT_SUBLIST_CONFIG(base, BASE);
> +KVM_SBI_EXT_SUBLIST_CONFIG(sta, STA);
>  KVM_SBI_EXT_SIMPLE_CONFIG(pmu, PMU);
>  KVM_SBI_EXT_SIMPLE_CONFIG(dbcn, DBCN);
>
> @@ -858,6 +900,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM);
>
>  struct vcpu_reg_list *vcpu_configs[] = {
>         &config_sbi_base,
> +       &config_sbi_sta,
>         &config_sbi_pmu,
>         &config_sbi_dbcn,
>         &config_aia,
> --
> 2.43.0
>