[PATCH v1 0/7] MPFS clock fixes required for correct CAN clock modeling

[Conor Dooley]

On Fri, Dec 08, 2023 at 05:07:39PM +0000, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley at microchip.com>
> 
> While reviewing a CAN clock driver internally for MPFS [1], I realised
> that the modeling of the MSSPLL such that one one of its outputs could
> be used was not correct. The CAN controllers on MPFS take 2 input
> clocks - one that is the bus clock, acquired from the main MSSPLL and
> a second clock for the AHB interface to the result of the SoC.
> Currently the binding for the CAN controllers and the represetnation
> of the MSSPLL only allows for one of these clocks.
> Modify the binding and devicetree to expect two clocks and rework the
> main clock controller driver for MPFS such that it is capable of
> providing multiple outputs from the MSSPLL.
> 
> Cheers,
> Conor.

Whoops, that was meant to get a dry run arg... Please ignore!
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