[PATCH v2 4/4] riscv: dts: sophgo: add uart clock for Sophgo CV1800 series SoC

[Inochi Amaoto]

>
>Inochi Amaoto wrote:
>> Add missing clocks of uart node for CV1800B and CV1812H.
>>
>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>> ---
>>  arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 21 ++++++++++++++++-----
>>  1 file changed, 16 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> index c5642dd7cbbd..3f290a515011 100644
>> --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
>> @@ -5,6 +5,7 @@
>>   */
>>
>>  #include <dt-bindings/interrupt-controller/irq.h>
>> +#include <dt-bindings/clock/sophgo,cv1800.h>
>>
>>  / {
>>  	#address-cells = <1>;
>> @@ -136,7 +137,9 @@ uart0: serial at 4140000 {
>>  			compatible = "snps,dw-apb-uart";
>>  			reg = <0x04140000 0x100>;
>>  			interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
>> -			clocks = <&osc>;
>> +			clock-frequency = <25000000>;
>> +			clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
>> +			clock-names = "baudclk", "apb_pclk";
>>  			reg-shift = <2>;
>>  			reg-io-width = <4>;
>>  			status = "disabled";
>
>Hi Inochi,
>
>When there is a proper "baudclk" defined the driver should get the rate
>(frequency) from that and the manually defined clock-frequency should not be
>needed.
>
>/Emil
>

OK, thanks, I will remove this.