[PATCH v5 1/2] dt-bindings: timer: thead,c900-aclint-mtimer: separate mtime and mtimecmp regs

[Inochi Amaoto]

>On Mon, Dec 04, 2023 at 05:39:09PM +0100, Daniel Lezcano wrote:
>> On 04/12/2023 17:18, Conor Dooley wrote:
>>> On Mon, Dec 04, 2023 at 05:51:08PM +0800, Inochi Amaoto wrote:
>>>> The timer registers of aclint don't follow the clint layout and can
>>>> be mapped on any different offset. As sg2042 uses separated timer
>>>> and mswi for its clint, it should follow the aclint spec and have
>>>> separated registers.
>>>>
>>>> The previous patch introduced a new type of T-HEAD aclint timer which
>>>> has clint timer layout. Although it has the clint timer layout, it
>>>> should follow the aclint spec and uses the separated mtime and mtimecmp
>>>> regs. So a ABI change is needed to make the timer fit the aclint spec.
>>>>
>>>> To make T-HEAD aclint timer more closer to the aclint spec, use
>>>> regs-names to represent the mtimecmp register, which can avoid hack
>>>> for unsupport mtime register of T-HEAD aclint timer.
>>>>
>>>> Also, as T-HEAD aclint only supports mtimecmp, it is unnecessary to
>>>> implement the whole aclint spec. To make this binding T-HEAD specific,
>>>> only add reg-name for existed register. For details, see the discussion
>>>> in the last link.
>>>>
>>>> Signed-off-by: Inochi Amaoto <inochiama at outlook.com>
>>>> Fixes: 4734449f7311 ("dt-bindings: timer: Add Sophgo sg2042 CLINT timer")
>>>> Link: https://lists.infradead.org/pipermail/opensbi/2023-October/005693.html
>>>> Link: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>>>> Link: https://lore.kernel.org/all/IA1PR20MB4953F9D77FFC76A9D236922DBBB6A@IA1PR20MB4953.namprd20.prod.outlook.com/
>>>
>>> Acked-by: Conor Dooley <conor.dooley at microchip.com>
>>>
>>> Although, I figure it is going to be me that ends up taking it.
>>
>> No, I should take it
>
>Sweet, I'd rather you took it than it went via a DT tree :)
>

Thanks you both for taking this. This is good news for me.