[PATCH v2 3/6] RISC-V: hwprobe: Expose Zicboz extension and its block size
Conor Dooley
conor at kernel.org
Thu Aug 31 09:19:55 PDT 2023
On Wed, Aug 30, 2023 at 06:49:58PM +0200, Andrew Jones wrote:
> Expose Zicboz through hwprobe and also provide a key to extract its
> respective block size. Opportunistically add a macro and apply it to
> current extensions in order to avoid duplicating code.
>
> Signed-off-by: Andrew Jones <ajones at ventanamicro.com>
> Reviewed-by: Evan Green <evan at rivosinc.com>
> ---
> Documentation/riscv/hwprobe.rst | 6 ++++
> arch/riscv/include/asm/hwprobe.h | 2 +-
> arch/riscv/include/uapi/asm/hwprobe.h | 2 ++
> arch/riscv/kernel/sys_riscv.c | 46 +++++++++++++++++++--------
> 4 files changed, 41 insertions(+), 15 deletions(-)
>
> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
> index 933c715065d6..6a17c2872660 100644
> --- a/Documentation/riscv/hwprobe.rst
> +++ b/Documentation/riscv/hwprobe.rst
> @@ -77,6 +77,9 @@ The following keys are defined:
> * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
> in version 1.0 of the Bit-Manipulation ISA extensions.
>
> + * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
> + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
> +
> * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
> information about the selected set of processors.
>
> @@ -97,3 +100,6 @@ The following keys are defined:
>
> * :c:macro:`RISCV_HWPROBE_MISALIGNED_UNSUPPORTED`: Misaligned accesses are
> not supported at all and will generate a misaligned address fault.
> +
> +* :c:macro:`RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE`: An unsigned int which
> + represents the size of the Zicboz block in bytes.
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 78936f4ff513..39df8604fea1 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,6 +8,6 @@
>
> #include <uapi/asm/hwprobe.h>
>
> -#define RISCV_HWPROBE_MAX_KEY 5
> +#define RISCV_HWPROBE_MAX_KEY 6
>
> #endif
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 006bfb48343d..86d08a0e617b 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -29,6 +29,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_EXT_ZBA (1 << 3)
> #define RISCV_HWPROBE_EXT_ZBB (1 << 4)
> #define RISCV_HWPROBE_EXT_ZBS (1 << 5)
> +#define RISCV_HWPROBE_EXT_ZICBOZ (1 << 6)
> #define RISCV_HWPROBE_KEY_CPUPERF_0 5
> #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
> #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
> @@ -36,6 +37,7 @@ struct riscv_hwprobe {
> #define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
> #define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
> #define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
> +#define RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE 6
> /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>
> #endif
> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> index 26ef5526bfb4..d17cb5b4945b 100644
> --- a/arch/riscv/kernel/sys_riscv.c
> +++ b/arch/riscv/kernel/sys_riscv.c
> @@ -145,26 +145,38 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> for_each_cpu(cpu, cpus) {
> struct riscv_isainfo *isainfo = &hart_isa[cpu];
>
> - if (riscv_isa_extension_available(isainfo->isa, ZBA))
> - pair->value |= RISCV_HWPROBE_EXT_ZBA;
> - else
> - missing |= RISCV_HWPROBE_EXT_ZBA;
> -
> - if (riscv_isa_extension_available(isainfo->isa, ZBB))
> - pair->value |= RISCV_HWPROBE_EXT_ZBB;
> - else
> - missing |= RISCV_HWPROBE_EXT_ZBB;
> -
> - if (riscv_isa_extension_available(isainfo->isa, ZBS))
> - pair->value |= RISCV_HWPROBE_EXT_ZBS;
> - else
> - missing |= RISCV_HWPROBE_EXT_ZBS;
> +#define EXT_KEY(ext) \
> + do { \
> + if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_EXT_##ext)) \
> + pair->value |= RISCV_HWPROBE_EXT_##ext; \
> + else \
> + missing |= RISCV_HWPROBE_EXT_##ext; \
> + } while (false)
> +
> + /*
> + * Only use EXT_KEY() for extensions which can be exposed to userspace,
> + * regardless of the kernel's configuration, as no other checks, besides
> + * presence in the hart_isa bitmap, are made.
Thanks for adding the comment.
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>
Thanks,
Conor.
> + */
> + EXT_KEY(ZBA);
> + EXT_KEY(ZBB);
> + EXT_KEY(ZBS);
> + EXT_KEY(ZICBOZ);
> +#undef EXT_KEY
> }
>
> /* Now turn off reporting features if any CPU is missing it. */
> pair->value &= ~missing;
> }
>
> +static bool hwprobe_ext0_has(const struct cpumask *cpus, unsigned long ext)
> +{
> + struct riscv_hwprobe pair;
> +
> + hwprobe_isa_ext0(&pair, cpus);
> + return (pair.value & ext);
> +}
> +
> static u64 hwprobe_misaligned(const struct cpumask *cpus)
> {
> int cpu;
> @@ -215,6 +227,12 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
> pair->value = hwprobe_misaligned(cpus);
> break;
>
> + case RISCV_HWPROBE_KEY_ZICBOZ_BLOCK_SIZE:
> + pair->value = 0;
> + if (hwprobe_ext0_has(cpus, RISCV_HWPROBE_EXT_ZICBOZ))
> + pair->value = riscv_cboz_block_size;
> + break;
> +
> /*
> * For forward compatibility, unknown keys don't fail the whole
> * call, but get their element key set to -1 and value set to 0
> --
> 2.41.0
>
>
> _______________________________________________
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> linux-riscv at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
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