[PATCH v2 0/6] RISC-V: Enable cbo.zero in usermode
Andrew Jones
ajones at ventanamicro.com
Wed Aug 30 09:49:55 PDT 2023
In order for usermode to issue cbo.zero, it needs privilege granted to
issue the extension instruction (patch 2) and to know that the extension
is available and its block size (patch 3). Patch 1 could be separate from
this series (it just fixes up some error messages), patches 4-5 convert
the hwprobe selftest to a statically-linked, TAP test and patch 6 adds a
new hwprobe test for the new information as well as testing CBO
instructions can or cannot be issued as appropriate.
Thanks,
drew
v2:
- fixed build of the vector selftest
- changed this-cpu wrappers to just cpu wrappers and then pass
smp_processor_id() at the callsite
- added comment to EXT_KEY macro
- picked up a couple r-b's
Andrew Jones (6):
RISC-V: Make zicbom/zicboz errors consistent
RISC-V: Enable cbo.zero in usermode
RISC-V: hwprobe: Expose Zicboz extension and its block size
RISC-V: selftests: Statically link hwprobe test
RISC-V: selftests: Convert hwprobe test to kselftest API
RISC-V: selftests: Add CBO tests
Documentation/riscv/hwprobe.rst | 6 +
arch/riscv/include/asm/cpufeature.h | 2 +
arch/riscv/include/asm/csr.h | 1 +
arch/riscv/include/asm/hwcap.h | 16 ++
arch/riscv/include/asm/hwprobe.h | 2 +-
arch/riscv/include/uapi/asm/hwprobe.h | 2 +
arch/riscv/kernel/cpufeature.c | 10 +-
arch/riscv/kernel/setup.c | 4 +
arch/riscv/kernel/smpboot.c | 4 +
arch/riscv/kernel/sys_riscv.c | 46 +++--
.../testing/selftests/riscv/hwprobe/Makefile | 9 +-
tools/testing/selftests/riscv/hwprobe/cbo.c | 162 ++++++++++++++++++
.../testing/selftests/riscv/hwprobe/hwprobe.c | 64 +++----
.../testing/selftests/riscv/hwprobe/hwprobe.h | 15 ++
14 files changed, 280 insertions(+), 63 deletions(-)
create mode 100644 tools/testing/selftests/riscv/hwprobe/cbo.c
create mode 100644 tools/testing/selftests/riscv/hwprobe/hwprobe.h
--
2.41.0
More information about the linux-riscv
mailing list