[PATCH] riscv: kprobes: allow writing to x0

[Charlie Jenkins]

On Tue, Aug 29, 2023 at 08:25:00PM +0200, Nam Cao wrote:
> Instructions can write to x0, so we should simulate these instructions
> normally.
> 
> Currently, the kernel hangs if an instruction who writes to x0 is
> simulated.
> 
> Fixes: c22b0bcb1dd0 ("riscv: Add kprobes supported")
> Cc: stable at vger.kernel.org
> Signed-off-by: Nam Cao <namcaov at gmail.com>
> ---
>  arch/riscv/kernel/probes/simulate-insn.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c
> index d3099d67816d..6c166029079c 100644
> --- a/arch/riscv/kernel/probes/simulate-insn.c
> +++ b/arch/riscv/kernel/probes/simulate-insn.c
> @@ -24,7 +24,7 @@ static inline bool rv_insn_reg_set_val(struct pt_regs *regs, u32 index,
>  				       unsigned long val)
>  {
>  	if (index == 0)
> -		return false;
> +		return true;
>  	else if (index <= 31)
>  		*((unsigned long *)regs + index) = val;
>  	else
> -- 
> 2.34.1
> 
> 
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Thank you for this change. 

simulate_auipc would previously fail with an rd = 0 which made sense
because auipc it is defined as a HINT in the riscv spec when rd = 0,
but QEMU and spike don't say it is an illegal instruction so I think
it is okay to make this change.

Reviewed-by: Charlie Jenkins <charlie at rivosinc.com>