[PATCH] RISC-V: Optimize bitops with Zbb extension

[Wang, Xiao W]

Hi,

A gentle ping.
Any other comments or suggestions for this patch? Or maybe we would review it in the Linux 6.7 development cycle?

BRs,
Xiao

> -----Original Message-----
> From: Wang, Xiao W
> Sent: Sunday, August 6, 2023 6:24 PM
> To: Ard Biesheuvel <ardb at kernel.org>
> Cc: paul.walmsley at sifive.com; palmer at dabbelt.com;
> aou at eecs.berkeley.edu; anup at brainfault.org; Li, Haicheng
> <haicheng.li at intel.com>; linux-riscv at lists.infradead.org; linux-
> efi at vger.kernel.org; linux-kernel at vger.kernel.org
> Subject: RE: [PATCH] RISC-V: Optimize bitops with Zbb extension
> 
> Hi,
> 
> > -----Original Message-----
> > From: Ard Biesheuvel <ardb at kernel.org>
> > Sent: Sunday, August 6, 2023 5:39 PM
> > To: Wang, Xiao W <xiao.w.wang at intel.com>
> > Cc: paul.walmsley at sifive.com; palmer at dabbelt.com;
> > aou at eecs.berkeley.edu; anup at brainfault.org; Li, Haicheng
> > <haicheng.li at intel.com>; linux-riscv at lists.infradead.org; linux-
> > efi at vger.kernel.org; linux-kernel at vger.kernel.org
> > Subject: Re: [PATCH] RISC-V: Optimize bitops with Zbb extension
> >
> > On Sun, 6 Aug 2023 at 04:39, Xiao Wang <xiao.w.wang at intel.com> wrote:
> > >
> > > This patch leverages the alternative mechanism to dynamically optimize
> > > bitops (including __ffs, __fls, ffs, fls) with Zbb instructions. When
> > > Zbb ext is not supported by the runtime CPU, legacy implementation is
> > > used. If Zbb is supported, then the optimized variants will be selected
> > > via alternative patching.
> > >
> > > The legacy bitops support is taken from the generic C implementation as
> > > fallback.
> > >
> > > If the parameter is a build-time constant, we leverage compiler builtin to
> > > calculate the result directly, this approach is inspired by x86 bitops
> > > implementation.
> > >
> > > EFI stub runs before the kernel, so alternative mechanism should not be
> > > used there, this patch introduces a macro EFI_NO_ALTERNATIVE for this
> > > purpose.
> > >
> >
> > Why? The unpatched sequences work fine, no?
> 
> It works. But there would be build warning: orphan section `.init.alternative'
> from `./drivers/firmware/efi/libstub/gop.stub.o' being placed in section
> `.init.alternative'. Besides, w/o this MACRO, the optimized variant would
> never be used at runtime, so this patch choose to disable alternative.
> 
> BRs,
> Xiao
> 
> >
> >
> > > Signed-off-by: Xiao Wang <xiao.w.wang at intel.com>
> > > ---
> > >  arch/riscv/include/asm/bitops.h       | 266
> +++++++++++++++++++++++++-
> > >  drivers/firmware/efi/libstub/Makefile |   2 +-
> > >  2 files changed, 264 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/arch/riscv/include/asm/bitops.h
> > b/arch/riscv/include/asm/bitops.h
> > > index 3540b690944b..f727f6489cd5 100644
> > > --- a/arch/riscv/include/asm/bitops.h
> > > +++ b/arch/riscv/include/asm/bitops.h
> > > @@ -15,13 +15,273 @@
> > >  #include <asm/barrier.h>
> > >  #include <asm/bitsperlong.h>
> > >
> > > +#if !defined(CONFIG_RISCV_ISA_ZBB) || defined(EFI_NO_ALTERNATIVE)
> > >  #include <asm-generic/bitops/__ffs.h>
> > > -#include <asm-generic/bitops/ffz.h>
> > > -#include <asm-generic/bitops/fls.h>
> > >  #include <asm-generic/bitops/__fls.h>
> > > +#include <asm-generic/bitops/ffs.h>
> > > +#include <asm-generic/bitops/fls.h>
> > > +
> > > +#else
> > > +#include <asm/alternative-macros.h>
> > > +#include <asm/hwcap.h>
> > > +
> > > +#if (BITS_PER_LONG == 64)
> > > +#define CTZW   "ctzw "
> > > +#define CLZW   "clzw "
> > > +#elif (BITS_PER_LONG == 32)
> > > +#define CTZW   "ctz "
> > > +#define CLZW   "clz "
> > > +#else
> > > +#error "Unexpected BITS_PER_LONG"
> > > +#endif
> [...]