[PATCH v4 17/36] arm64/mm: Handle GCS data aborts

[Catalin Marinas]

On Mon, Aug 07, 2023 at 11:00:22PM +0100, Mark Brown wrote:
> @@ -510,6 +527,26 @@ static vm_fault_t __do_page_fault(struct mm_struct *mm,
>  	 */
>  	if (!(vma->vm_flags & vm_flags))
>  		return VM_FAULT_BADACCESS;
> +
> +	if (vma->vm_flags & VM_SHADOW_STACK) {
> +		/*
> +		 * Writes to a GCS must either be generated by a GCS
> +		 * operation or be from EL1.
> +		 */
> +		if (is_write_abort(esr) &&
> +		    !(is_gcs_fault(esr) || is_el1_data_abort(esr)))
> +			return VM_FAULT_BADACCESS;

Related to my PIE permissions comment: when do we have a valid EL1 data
write abort that's not a GCS fault? Does a faulting GCSSTTR set the
ESR_ELx_GCS bit?

> +	} else {
> +		/*
> +		 * GCS faults should never happen for pages that are
> +		 * not part of a GCS and the operation being attempted
> +		 * can never succeed.
> +		 */
> +		if (is_gcs_fault(esr))
> +			return VM_FAULT_BADACCESS;

If one does a GCS push/store to a non-GCS page, do we get a GCS fault or
something else? I couldn't figure out from the engineering spec. If the
hardware doesn't generate such exceptions, we might as well remove this
'else' branch. But maybe it does generate a GCS-specific fault as you
added a similar check in is_invalid_el0_gcs_access().

> @@ -595,6 +644,19 @@ static int __kprobes do_page_fault(unsigned long far, unsigned long esr,
>  	if (!vma)
>  		goto lock_mmap;
>  
> +	/*
> +	 * We get legitimate write faults for GCS pages from GCS
> +	 * operations and from EL1 writes to EL0 pages but just plain

What are the EL1 writes to the shadow stack? Would it not use
copy_to_user_gcs()?

-- 
Catalin