[PATCH 2/6] RISC-V: Enable cbo.zero in usermode

[Evan Green]

On Wed, Aug 9, 2023 at 4:55 AM Andrew Jones <ajones at ventanamicro.com> wrote:
>
> When Zicboz is present, enable its instruction (cbo.zero) in
> usermode by setting its respective senvcfg bit. We don't bother
> trying to set this bit per-task, which would also require an
> interface for tasks to request enabling and/or disabling. Instead,
> permanently set the bit for each hart which has the extension when
> bringing it online.
>
> Signed-off-by: Andrew Jones <ajones at ventanamicro.com>
> ---
>  arch/riscv/include/asm/cpufeature.h |  2 ++
>  arch/riscv/include/asm/csr.h        |  1 +
>  arch/riscv/include/asm/hwcap.h      | 16 ++++++++++++++++
>  arch/riscv/kernel/cpufeature.c      |  6 ++++++
>  arch/riscv/kernel/setup.c           |  4 ++++
>  arch/riscv/kernel/smpboot.c         |  4 ++++
>  6 files changed, 33 insertions(+)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 23fed53b8815..788fd575c21a 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -30,4 +30,6 @@ DECLARE_PER_CPU(long, misaligned_access_speed);
>  /* Per-cpu ISA extensions. */
>  extern struct riscv_isainfo hart_isa[NR_CPUS];
>
> +void riscv_user_isa_enable(void);
> +
>  #endif
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 7bac43a3176e..e187e76e3df4 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -273,6 +273,7 @@
>  #define CSR_SIE                        0x104
>  #define CSR_STVEC              0x105
>  #define CSR_SCOUNTEREN         0x106
> +#define CSR_SENVCFG            0x10a
>  #define CSR_SSCRATCH           0x140
>  #define CSR_SEPC               0x141
>  #define CSR_SCAUSE             0x142
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index f041bfa7f6a0..4929faecb75f 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -66,6 +66,7 @@
>  #ifndef __ASSEMBLY__
>
>  #include <linux/jump_label.h>
> +#include <asm/cpufeature.h>
>
>  unsigned long riscv_get_elf_hwcap(void);
>
> @@ -130,6 +131,21 @@ riscv_has_extension_unlikely(const unsigned long ext)
>         return true;
>  }
>
> +static __always_inline bool riscv_this_cpu_has_extension_likely(const unsigned long ext)
> +{
> +       if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
> +               return true;
> +
> +       return __riscv_isa_extension_available(hart_isa[smp_processor_id()].isa, ext);
> +}
> +
> +static __always_inline bool riscv_this_cpu_has_extension_unlikely(const unsigned long ext)
> +{
> +       if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
> +               return true;
> +
> +       return __riscv_isa_extension_available(hart_isa[smp_processor_id()].isa, ext);
> +}

Another way to do this would be to add a parameter to
riscv_has_extension_*() (as there are very few users), then these new
functions can turn around and call those with the new parameter set to
hart_isa[smp_processor_id()].isa. It's a tossup, so up to you. The
only advantage to it I can argue is it keeps the code flows more
unified.

-Evan