[PATCH v2 1/1] RISC-V: KVM: provide UAPI for host SATP mode

[Anup Patel]

On Sat, Jul 29, 2023 at 2:31 AM Daniel Henrique Barboza
<dbarboza at ventanamicro.com> wrote:
>
> KVM userspaces need to be aware of the host SATP to allow them to
> advertise it back to the guest OS.
>
> Since this information is used to build the guest FDT we can't wait for
> the SATP reg to be readable. We just need to read the SATP mode, thus
> we can use the existing 'satp_mode' global that represents the SATP reg
> with MODE set and both ASID and PPN cleared. E.g. for a 32 bit host
> running with sv32 satp_mode is 0x80000000, for a 64 bit host running
> sv57 satp_mode is 0xa000000000000000, and so on.
>
> Add a new userspace virtual config register 'satp_mode' to allow
> userspace to read the current SATP mode the host is using with
> GET_ONE_REG API before spinning the vcpu.
>
> 'satp_mode' can't be changed via KVM, so SET_ONE_REG is allowed as long
> as userspace writes the existing 'satp_mode'.
>
> Signed-off-by: Daniel Henrique Barboza <dbarboza at ventanamicro.com>
> Reviewed-by: Andrew Jones <ajones at ventanamicro.com>

Queued this patch for Linux-6.6

Thanks,
Anup

> ---
>  arch/riscv/include/asm/csr.h      | 2 ++
>  arch/riscv/include/uapi/asm/kvm.h | 1 +
>  arch/riscv/kvm/vcpu_onereg.c      | 7 +++++++
>  3 files changed, 10 insertions(+)
>
> diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
> index 7bac43a3176e..777cb8299551 100644
> --- a/arch/riscv/include/asm/csr.h
> +++ b/arch/riscv/include/asm/csr.h
> @@ -54,6 +54,7 @@
>  #ifndef CONFIG_64BIT
>  #define SATP_PPN       _AC(0x003FFFFF, UL)
>  #define SATP_MODE_32   _AC(0x80000000, UL)
> +#define SATP_MODE_SHIFT        31
>  #define SATP_ASID_BITS 9
>  #define SATP_ASID_SHIFT        22
>  #define SATP_ASID_MASK _AC(0x1FF, UL)
> @@ -62,6 +63,7 @@
>  #define SATP_MODE_39   _AC(0x8000000000000000, UL)
>  #define SATP_MODE_48   _AC(0x9000000000000000, UL)
>  #define SATP_MODE_57   _AC(0xa000000000000000, UL)
> +#define SATP_MODE_SHIFT        60
>  #define SATP_ASID_BITS 16
>  #define SATP_ASID_SHIFT        44
>  #define SATP_ASID_MASK _AC(0xFFFF, UL)
> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h
> index 9c35e1427f73..992c5e407104 100644
> --- a/arch/riscv/include/uapi/asm/kvm.h
> +++ b/arch/riscv/include/uapi/asm/kvm.h
> @@ -55,6 +55,7 @@ struct kvm_riscv_config {
>         unsigned long marchid;
>         unsigned long mimpid;
>         unsigned long zicboz_block_size;
> +       unsigned long satp_mode;
>  };
>
>  /* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c
> index 0dc2c2cecb45..85773e858120 100644
> --- a/arch/riscv/kvm/vcpu_onereg.c
> +++ b/arch/riscv/kvm/vcpu_onereg.c
> @@ -152,6 +152,9 @@ static int kvm_riscv_vcpu_get_reg_config(struct kvm_vcpu *vcpu,
>         case KVM_REG_RISCV_CONFIG_REG(mimpid):
>                 reg_val = vcpu->arch.mimpid;
>                 break;
> +       case KVM_REG_RISCV_CONFIG_REG(satp_mode):
> +               reg_val = satp_mode >> SATP_MODE_SHIFT;
> +               break;
>         default:
>                 return -EINVAL;
>         }
> @@ -234,6 +237,10 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu,
>                 else
>                         return -EBUSY;
>                 break;
> +       case KVM_REG_RISCV_CONFIG_REG(satp_mode):
> +               if (reg_val != (satp_mode >> SATP_MODE_SHIFT))
> +                       return -EINVAL;
> +               break;
>         default:
>                 return -EINVAL;
>         }
> --
> 2.41.0
>