[PATCH 2/3] RISC-V: Track ISA extensions per hart

[Conor Dooley]

On Fri, Apr 28, 2023 at 12:06:07PM -0700, Evan Green wrote:

> @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
>  	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>  
>  	for_each_of_cpu_node(node) {
> +		struct riscv_isainfo *isainfo;
>  		unsigned long this_hwcap = 0;
> -		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
>  		const char *temp;
> +		unsigned int cpu_id;
>  
>  		rc = riscv_of_processor_hartid(node, &hartid);
>  		if (rc < 0)
>  			continue;
>  
> +		cpu_id = riscv_hartid_to_cpuid(hartid);
> +		isainfo = &hart_isa[cpu_id];
>  		if (of_property_read_string(node, "riscv,isa", &isa)) {

Would you mind adding a blank line above the if statement please?
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

Thanks,
Conor.

>  			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
>  			continue;
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