[PATCH] RISC-V: Re-enable counter access from userspace

[Conor Dooley]

On Wed, Sep 28, 2022 at 06:18:07AM -0700, Palmer Dabbelt wrote:
> These counters were part of the ISA when we froze the uABI, removing
> them breaks userspace.
> 
> Link: https://lore.kernel.org/all/YxEhC%2FmDW1lFt36J@aurel32.net/
> Fixes: e9991434596f ("RISC-V: Add perf platform driver based on SBI PMU extension")

At the risk of stating the obvious, I assume this will also be CC:stable
when you apply it since this goes back as far as (I think) 5.18?

Thanks,
Conor.

> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>
> ---
>  drivers/perf/riscv_pmu_sbi.c | 7 +++++--
>  1 file changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c
> index 6f6681bbfd36..e45daffbfb36 100644
> --- a/drivers/perf/riscv_pmu_sbi.c
> +++ b/drivers/perf/riscv_pmu_sbi.c
> @@ -645,8 +645,11 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node)
>  	struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node);
>  	struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events);
>  
> -	/* Enable the access for TIME csr only from the user mode now */
> -	csr_write(CSR_SCOUNTEREN, 0x2);
> +	/*
> +	 * Enable the access for CYCLE, TIME, and INSTRET CSRs from userspace,
> +	 * as is necessary to maintain uABI compatibility.
> +	 */
> +	csr_write(CSR_SCOUNTEREN, 0x7);
>  
>  	/* Stop all the counters so that they can be enabled from perf */
>  	pmu_sbi_stop_all(pmu);
> -- 
> 2.34.1
> 
> 
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