[PATCH] RISC-V: Print SSTC in canonical order

[Conor Dooley]

On Tue, Sep 20, 2022 at 01:45:18PM -0700, Palmer Dabbelt wrote:
> This got out of order during a merge conflict, fix it by putting the
> entries in the correct order.
> 
> Fixes: 7ab52f75a9cf ("RISC-V: Add Sstc extension support")
> Signed-off-by: Palmer Dabbelt <palmer at rivosinc.com>

My OCD is a fan of this patch, so on that basis:
Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

> ---
>  arch/riscv/kernel/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 0be8a2403212..87455d12970f 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -92,10 +92,10 @@ int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid)
>   */
>  static struct riscv_isa_ext_data isa_ext_arr[] = {
>  	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
> +	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
>  	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> -	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
>  	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),
>  };
>  
> -- 
> 2.34.1
> 
> 
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