[PATCH v2] serial: sifive: enable clocks for UART when probed

[Palmer Dabbelt]

On Tue, 20 Sep 2022 09:00:18 PDT (-0700), Olof Johansson wrote:
> When the PWM driver was changed to disable clocks if no PWMs are enabled,
> it ended up also disabling the shared parent with the UART, since the
> UART doesn't do any clock enablement on its own.
>
> To avoid these surprises, switch to clk_get_enabled().
>
> Fixes: ace41d7564e655 ("pwm: sifive: Ensure the clk is enabled exactly once per running PWM")
> Cc: Uwe Kleine-König <u.kleine-koenig at pengutronix.de>
> Cc: Emil Renner Berthing <emil.renner.berthing at canonical.com>
> Cc: Palmer Dabbelt <palmer at dabbelt.com>
> Cc: Paul Walmsley <paul.walmsley at sifive.com>
> Signed-off-by: Olof Johansson <olof at lixom.net>
>
> ---
>
> v2: Switch to devm_clk_enabled() per Uwe's suggestion.
>
> ---
>  drivers/tty/serial/sifive.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
> index 5c3a07546a58..4b1d4fe8458e 100644
> --- a/drivers/tty/serial/sifive.c
> +++ b/drivers/tty/serial/sifive.c
> @@ -945,7 +945,7 @@ static int sifive_serial_probe(struct platform_device *pdev)
>  		return PTR_ERR(base);
>  	}
>
> -	clk = devm_clk_get(&pdev->dev, NULL);
> +	clk = devm_clk_get_enabled(&pdev->dev, NULL);
>  	if (IS_ERR(clk)) {
>  		dev_err(&pdev->dev, "unable to find controller clock\n");
>  		return PTR_ERR(clk);

I have one of these lying around somewhere if you need someone to test 
it, but sounds like you had from the v1 email.  Either way

Acked-by: Palmer Dabbelt <palmer at rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer at rivosinc.com>

as this seems better than what was there.

Thanks!