[PATCH v4 00/10] Add support for Renesas RZ/Five SoC

[Conor Dooley]

On Tue, Sep 20, 2022 at 09:24:05PM +0200, Geert Uytterhoeven wrote:
> Hi Conor,
> 
> On Tue, Sep 20, 2022 at 9:20 PM Conor Dooley <conor at kernel.org> wrote:
> > On Tue, Sep 20, 2022 at 07:48:54PM +0100, Prabhakar wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> > > The RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single)
> > > 1.0 GHz, 16-bit DDR3L/DDR4 interface. And it also has many interfaces such
> > > as Gbit-Ether, CAN, and USB 2.0, making it ideal for applications such as
> > > entry-class social infrastructure gateway control and industrial gateway
> > > control.
> > >
> > > This patch series adds initial SoC DTSi support for Renesas RZ/Five
> > > (R9A07G043) SoC and updates the bindings for the same. Below is the list
> > > of IP blocks added in the initial SoC DTSI which can be used to boot via
> > > initramfs on RZ/Five SMARC EVK:
> > > - AX45MP CPU
> > > - CPG
> > > - PINCTRL
> > > - PLIC
> > > - SCIF0
> > > - SYSC
> >
> > Ran into one complaint from dtbs_check:
> > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy at 11c50200: '#phy-cells' is a required property
> >         From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> > arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dtb: usb-phy at 11c70200: '#phy-cells' is a required property
> >         From schema: /home/conor/.local/lib/python3.10/site-packages/dtschema/schemas/phy/phy-provider.yaml
> >
> > Other than that which should be a trivial fix the whole lot looks good
> > to me...
> 
> That's due to the placeholders...

Right, but #phy-cells will be added into the usb-phys once you (plural)
figure out how to integrate with the existing CMO stuff?

> Currently it is not yet a requirement that "make dtbs_check" is warning-free.

I was really hoping that it could be a requirement for 6.1 onwards. I've
managed to clear all of the other ones from arch/riscv.

> I'm wondering how we have to handle new SoCs with existing boards in
> the future. Probably just more properties in the placeholders...

New SoCs to existing boards is less of a problem then new CPUs to
existing SoCs from what I can see...
I know we just discussed it earlier today, but is it possible to make
these particular placeholders more complete so that dtbs_check shuts up
about them?

Thanks,
Conor.