[PATCH v2] riscv: make update_mmu_cache to support asid

[Jinyu Tang]

At 2022-09-12 15:26:00, "Sergey Matyukevich" <geomatsi at gmail.com> wrote:
>Hi Jinyu,
>
>> The `update_mmu_cache` function in riscv flush tlb cache without asid
>> information now, which will flush tlbs in other tasks' address space
>> even if processor supports asid. So add a new function
>> `flush_tlb_local_one_page` to flush local one page whether processor
>> supports asid or not,for cases that need to flush local one page like
>> function `update_mmu_cache`.
>> 
>> Signed-off-by: Jinyu Tang <tjytimi at 163.com>
>> ---
>> RFC V1 -> V2 : 
>> 1.Rebased on PATCH9 of IPI imporvement series as Anup Patel
>> suggestion. 
>> 2.Make commit log more clear.
>> 
>>  arch/riscv/include/asm/pgtable.h  |  2 +-
>>  arch/riscv/include/asm/tlbflush.h |  2 ++
>>  arch/riscv/mm/tlbflush.c          | 11 +++++++++++
>>  3 files changed, 14 insertions(+), 1 deletion(-)
>
>Just FYI: I have been looking into the same function w.r.t. to its
>ASID/SMP handling. In addition to what your patch is doing with ASID,
>I posted experimental change following flush_icache_mm approach. That
>patch takes into account other concurrently running harts as well as
>possible migration to other harts later on, see:
>
>https://lore.kernel.org/linux-riscv/20220829205219.283543-1-geomatsi@gmail.com/
>
>Regards,
>Sergey
Maybe local flush is enough for this function,because others may not use the pte forever.
And if another hart use this pte later, it may trap in pagefault to survive.

Yours,

Jinyu