[PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically

[Heiko Stuebner]

Am Donnerstag, 15. September 2022, 20:15:50 CEST schrieb Prabhakar:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Sort the CPU cores list alphabetically for maintenance.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>

That makes a lot of sense

Reviewed-by: Heiko Stuebner <heiko at sntech.de>

> ---
> v2->v3
> * included RB tag from Geert
> 
> v1->v2
> * Included RB tag from Krzysztof
> ---
>  Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index 873dd12f6e89..2a1c5ae5b0aa 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -27,17 +27,17 @@ properties:
>      oneOf:
>        - items:
>            - enum:
> -              - sifive,rocket0
> +              - canaan,k210
>                - sifive,bullet0
>                - sifive,e5
>                - sifive,e7
>                - sifive,e71
> -              - sifive,u74-mc
> -              - sifive,u54
> -              - sifive,u74
> +              - sifive,rocket0
>                - sifive,u5
> +              - sifive,u54
>                - sifive,u7
> -              - canaan,k210
> +              - sifive,u74
> +              - sifive,u74-mc
>            - const: riscv
>        - items:
>            - enum:
>