[PATCH v4 0/3] perf: RISC-V: misc fixes and improvements

[Palmer Dabbelt]

On Tue, 30 Aug 2022 08:53:03 PDT (-0700), geomatsi at gmail.com wrote:
> Hi all,
>
> Another respin: updated commit message and more RB tags.
>
> Regards,
> Sergey
>
> v3 -> v4:
> - added Fixes info to the first patch
> - updated commt message for the first patch
> - added RB tags by Atish Patra to the remaining patches
>
> v2 -> v3:
> - rebased on top of for-next branch in riscv kernel tree
> - added RB tag by Atish Patra to the first patch
> - added perf throttle patch
>
> v1 -> v2:
> - drop changes for access to the highest available counter as they are
>   now handled on the OpenSBI side
> - drop switch to IDR: in fact there is no need to handle non-contiguous
>   counter ranges
>
>
> Sergey Matyukevich (3):
>   perf: RISC-V: fix access beyond allocated array
>   perf: RISC-V: exclude invalid pmu counters from SBI calls
>   perf: RISC-V: throttle perf events
>
>  drivers/perf/riscv_pmu_legacy.c |  4 ++--
>  drivers/perf/riscv_pmu_sbi.c    | 33 +++++++++++++++++++++------------
>  include/linux/perf/riscv_pmu.h  |  2 +-
>  3 files changed, 24 insertions(+), 15 deletions(-)

I think only the first one here is a fix, the others are the 
improvements.  So I split this up and put the first on fixes, the others 
on for-next.

Thanks!