[PATCH v2 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache

[Conor.Dooley at microchip.com]

On 08/09/2022 22:21, Rob Herring wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On Mon, 05 Sep 2022 08:31:20 +0000, Zong Li wrote:
>> Since composable cache may be L3 cache if private L2 cache exists, we
>> should use its original name Composable cache to prevent confusion.
>>
>> Signed-off-by: Zong Li <zong.li at sifive.com>
>> Suggested-by: Conor Dooley <conor.dooley at microchip.com>
>> Suggested-by: Ben Dooks <ben.dooks at sifive.com>
>> ---
>>  ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++----
>>  1 file changed, 23 insertions(+), 5 deletions(-)
>>  rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%)
>>
> 
> Reviewed-by: Rob Herring <robh at kernel.org>

FWIW this was respun today:
https://lore.kernel.org/linux-riscv/20220908144424.4232-1-zong.li@sifive.com/

Content of this patch should be no different.