[PATCH v9 1/7] RISC-V: Clear SIP bit only when using SBI IPI operations

[Marc Zyngier]

On Sat, 03 Sep 2022 17:13:03 +0100,
Anup Patel <apatel at ventanamicro.com> wrote:
> 
> The software interrupt pending (i.e. [M|S]SIP) bit is writeable for
> S-mode but read-only for M-mode so we clear this bit only when using
> SBI IPI operations.
> 
> Signed-off-by: Anup Patel <apatel at ventanamicro.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
>  arch/riscv/kernel/sbi.c | 8 +++++++-
>  arch/riscv/kernel/smp.c | 2 --
>  2 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c
> index 775d3322b422..fc614650a2e3 100644
> --- a/arch/riscv/kernel/sbi.c
> +++ b/arch/riscv/kernel/sbi.c
> @@ -643,8 +643,14 @@ static void sbi_send_cpumask_ipi(const struct cpumask *target)
>  	sbi_send_ipi(target);
>  }
>  
> +static void sbi_ipi_clear(void)
> +{
> +	csr_clear(CSR_IP, IE_SIE);
> +}
> +
>  static const struct riscv_ipi_ops sbi_ipi_ops = {
> -	.ipi_inject = sbi_send_cpumask_ipi
> +	.ipi_inject = sbi_send_cpumask_ipi,
> +	.ipi_clear = sbi_ipi_clear
>  };
>  
>  void __init sbi_init(void)
> diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c
> index 760a64518c58..c56d67f53ea9 100644
> --- a/arch/riscv/kernel/smp.c
> +++ b/arch/riscv/kernel/smp.c
> @@ -83,8 +83,6 @@ void riscv_clear_ipi(void)
>  {
>  	if (ipi_ops && ipi_ops->ipi_clear)
>  		ipi_ops->ipi_clear();
> -
> -	csr_clear(CSR_IP, IE_SIE);
>  }
>  EXPORT_SYMBOL_GPL(riscv_clear_ipi);

This really begs the question: why on Earth are these things exported
to *modules*? I cannot see a good reason why they should be...

	M>

-- 
Without deviation from the norm, progress is not possible.