[PATCH v1 3/3] riscv: dts: microchip: add a devicetree for the Aldec TySoM

[Conor.Dooley at microchip.com]

On 06/09/2022 14:11, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> On 06/09/2022 14:15, Conor Dooley wrote:
>> The TySOM-M-MPFS250 is a compact SoC prototyping board featuring
>> a Microchip PolarFire SoC MPFS250T-FCG1152. Features include:
>> - 16 GB FPGA DDR4
>> - 16 GB MSS DDR4 with ECC
>> - eMMC
>> - SPI flash memory
>> - 2x Ethernet 10/100/1000
>> - USB 2.0
>> - PCIe x4 Gen2
>> - HDMI OUT
>> - 2x FMC connector (HPC and LPC)

>> +
>> +&spi1 {
>> +     status = "okay";
>> +     flash at 0 {
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
> 
> Are these needed? Does it pass dtbs_check?

It did, yea. But you're right in that they're not needed, I deleted some
dummy flash partitions that were in the dts I received and I didn't see
the cells too.

I'm likely going to sit on this patch for quite a while, but the various
things you pointed out all are valid, so they'll be sorted by the
eventual v2...

As always, thanks!

> 
>> +             compatible = "micron,n25q128a11", "jedec,spi-nor";
>> +             status = "okay";
> 
> No need for status.