[PATCH 1/3] RISC-V: Output cbom-block-size
Andrew Jones
ajones at ventanamicro.com
Tue Sep 6 02:01:24 PDT 2022
On Tue, Sep 06, 2022 at 10:55:33AM +0200, Andrew Jones wrote:
> On Tue, Sep 06, 2022 at 08:40:23AM +0000, Conor.Dooley at microchip.com wrote:
> > On 06/09/2022 09:35, Andrew Jones wrote:
> > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > >
> > > Provide an info message with the block size when the Zicbom extension is
> > > present and the block size has been determined.
> >
> > Why might someone care about this?
>
> I was unaware of anywhere else besides hardware descriptions where this is
> published. And, while dmesg isn't really publishing it in a way that is
> useful to anything other than human readers either, it at least makes it
> easy for a user to check it for sanity purposes (which is what I used it
> for) or even for applying it if they want to write something that needs it
> and the OS provides U-mode access to CMO.
Of course for applying it in U-mode programs it'd probably be better to
introduce a sysconf variable or similar to get it.
drew
>
> I'm not married to the idea, though, so if people would rather have less
> logs than this information, then I'm fine with dropping the patch.
>
> Thanks,
> drew
>
> >
> > >
> > > Signed-off-by: Andrew Jones <ajones at ventanamicro.com>
> > > ---
> > > arch/riscv/mm/cacheflush.c | 4 +++-
> > > 1 file changed, 3 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> > > index e5b087be1577..8595baf8e403 100644
> > > --- a/arch/riscv/mm/cacheflush.c
> > > +++ b/arch/riscv/mm/cacheflush.c
> > > @@ -122,7 +122,9 @@ void riscv_init_cbom_blocksize(void)
> > > }
> > > }
> > >
> > > - if (probed_block_size)
> > > + if (probed_block_size) {
> > > riscv_cbom_block_size = probed_block_size;
> > > + pr_info("riscv: Zicbom: Cache blocksize is %u bytes", probed_block_size);
> > > + }
> > > }
> > > #endif
> > > --
> > > 2.37.2
> > >
> >
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