[PATCH v2 4/6] soc: sifive: ccache: reduce printing on init

[Zong Li]

<Conor.Dooley at microchip.com> 於 2022年9月6日 週二 凌晨3:18寫道：
>
> On 05/09/2022 09:31, Zong Li wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> >
> > From: Ben Dooks <ben.dooks at sifive.com>
> >
> > The driver prints out 6 lines on startup, which can easily be redcued
> > to two lines without losing any information.
> >
> > Note, to make the types work better, uint64_t has been replaced with
> > ULL to make the unsigned long long match the format in the print
> > statement.
> >
> > Signed-off-by: Ben Dooks <ben.dooks at sifive.com>
>
> Hey Zong,
> Missing your SoB after Ben's here btw.
>

Ok, I would add it in V3.

> > ---
> >  drivers/soc/sifive/sifive_ccache.c | 25 +++++++++++--------------
> >  1 file changed, 11 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c
> > index 0e0eb85c94d8..401c67a485e2 100644
> > --- a/drivers/soc/sifive/sifive_ccache.c
> > +++ b/drivers/soc/sifive/sifive_ccache.c
> > @@ -81,20 +81,17 @@ static void setup_sifive_debug(void)
> >
> >  static void ccache_config_read(void)
> >  {
> > -       u32 regval, val;
> > -
> > -       regval = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> > -       val = regval & 0xFF;
> > -       pr_info("CCACHE: No. of Banks in the cache: %d\n", val);
> > -       val = (regval & 0xFF00) >> 8;
> > -       pr_info("CCACHE: No. of ways per bank: %d\n", val);
> > -       val = (regval & 0xFF0000) >> 16;
> > -       pr_info("CCACHE: Sets per bank: %llu\n", (uint64_t)1 << val);
> > -       val = (regval & 0xFF000000) >> 24;
> > -       pr_info("CCACHE: Bytes per cache block: %llu\n", (uint64_t)1 << val);
> > -
> > -       regval = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > -       pr_info("CCACHE: Index of the largest way enabled: %d\n", regval);
> > +       u32 cfg;
> > +
> > +       cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG);
> > +
> > +       pr_info("CCACHE: %u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n",
> > +               (cfg & 0xff), (cfg >> 8) & 0xff,
> > +               BIT_ULL((cfg >> 16) & 0xff),
> > +               BIT_ULL((cfg >> 24) & 0xff));
>
> Could we use defines please for the register shifts please?
>

Yes, let me define them in V3

> > +
> > +       cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE);
> > +       pr_info("CCACHE: Index of the largest way enabled: %d\n", cfg);
>
> %u here no?

Thanks for point it out. I would change it in V3.

> Thanks,
> Conor.
>
> >  }
> >
> >  static const struct of_device_id sifive_ccache_ids[] = {
> > --
> > 2.17.1
> >
>