[PATCH 2/4] riscv: drop some idefs from CMO initialization

[Conor.Dooley at microchip.com]

On 01/09/2022 23:27, Heiko Stuebner wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> 
> Wrapping things in #ifdefs makes the code harder to read
> while we also have IS_ENABLED() macros to do this in regular code
> and the extension detection is not _that_ runtime critical.
> 
> So define a stub for riscv_noncoherent_supported() in the
> non-CONFIG_RISCV_DMA_NONCOHERENT case and move the code to
> us IS_ENABLED.
> 
> Suggested-by: Conor Dooley <conor.dooley at microchip.com>

To my "sensitive" eyes, this looks a lot nicer!

Reviewed-by: Conor Dooley <conor.dooley at microchip.com>

> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> ---
>   arch/riscv/errata/thead/errata.c    |  7 +++----
>   arch/riscv/include/asm/cacheflush.h |  2 ++
>   arch/riscv/kernel/cpufeature.c      | 22 +++++++++-------------
>   3 files changed, 14 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> index 202c83f677b2..bffa711aaf64 100644
> --- a/arch/riscv/errata/thead/errata.c
> +++ b/arch/riscv/errata/thead/errata.c
> @@ -30,7 +30,9 @@ static bool errata_probe_pbmt(unsigned int stage,
>   static bool errata_probe_cmo(unsigned int stage,
>                               unsigned long arch_id, unsigned long impid)
>   {
> -#ifdef CONFIG_ERRATA_THEAD_CMO
> +       if (!IS_ENABLED(CONFIG_ERRATA_THEAD_CMO))
> +               return false;
> +
>          if (arch_id != 0 || impid != 0)
>                  return false;
> 
> @@ -39,9 +41,6 @@ static bool errata_probe_cmo(unsigned int stage,
> 
>          riscv_noncoherent_supported();
>          return true;
> -#else
> -       return false;
> -#endif
>   }
> 
>   static u32 thead_errata_probe(unsigned int stage,
> diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> index a60acaecfeda..4363d0beb38a 100644
> --- a/arch/riscv/include/asm/cacheflush.h
> +++ b/arch/riscv/include/asm/cacheflush.h
> @@ -50,6 +50,8 @@ static inline void riscv_init_cbom_blocksize(void) { }
> 
>   #ifdef CONFIG_RISCV_DMA_NONCOHERENT
>   void riscv_noncoherent_supported(void);
> +#else
> +static inline void riscv_noncoherent_supported(void) {}
>   #endif
> 
>   /*
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 764ea220161f..729f7a218093 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -264,21 +264,17 @@ static bool __init_or_module cpufeature_probe_svpbmt(unsigned int stage)
> 
>   static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage)
>   {
> -#ifdef CONFIG_RISCV_ISA_ZICBOM
> -       switch (stage) {
> -       case RISCV_ALTERNATIVES_EARLY_BOOT:
> +       if (!IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM))
> +               return false;
> +
> +       if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +               return false;
> +
> +       if (!riscv_isa_extension_available(NULL, ZICBOM))
>                  return false;
> -       default:
> -               if (riscv_isa_extension_available(NULL, ZICBOM)) {
> -                       riscv_noncoherent_supported();
> -                       return true;
> -               } else {
> -                       return false;
> -               }
> -       }
> -#endif
> 
> -       return false;
> +       riscv_noncoherent_supported();
> +       return true;
>   }
> 
>   /*
> --
> 2.35.1
>