[PATCH] riscv: Fix build with CONFIG_CC_OPTIMIZE_FOR_SIZE=y

[Palmer Dabbelt]

On Wed, 05 Oct 2022 23:48:11 PDT (-0700), jszhang at kernel.org wrote:
> On Thu, Sep 22, 2022 at 01:09:58AM -0500, Samuel Holland wrote:
>> commit 8eb060e10185 ("arch/riscv: add Zihintpause support") broke
>> building with CONFIG_CC_OPTIMIZE_FOR_SIZE enabled (gcc 11.1.0):
>>
>>   CC      arch/riscv/kernel/vdso/vgettimeofday.o
>> In file included from <command-line>:
>> ./arch/riscv/include/asm/jump_label.h: In function 'cpu_relax':
>> ././include/linux/compiler_types.h:285:33: warning: 'asm' operand 0 probably does not match constraints
>>   285 | #define asm_volatile_goto(x...) asm goto(x)
>>       |                                 ^~~
>> ./arch/riscv/include/asm/jump_label.h:41:9: note: in expansion of macro 'asm_volatile_goto'
>>    41 |         asm_volatile_goto(
>>       |         ^~~~~~~~~~~~~~~~~
>> ././include/linux/compiler_types.h:285:33: error: impossible constraint in 'asm'
>>   285 | #define asm_volatile_goto(x...) asm goto(x)
>>       |                                 ^~~
>> ./arch/riscv/include/asm/jump_label.h:41:9: note: in expansion of macro 'asm_volatile_goto'
>>    41 |         asm_volatile_goto(
>>       |         ^~~~~~~~~~~~~~~~~
>> make[1]: *** [scripts/Makefile.build:249: arch/riscv/kernel/vdso/vgettimeofday.o] Error 1
>> make: *** [arch/riscv/Makefile:128: vdso_prepare] Error 2
>>
>> Having a static branch in cpu_relax() is problematic because that
>> function is widely inlined, including in some quite complex functions
>> like in the VDSO. A quick measurement shows this static branch is
>> responsible by itself for around 40% of the jump table.
>>
>> Drop the static branch, which ends up being the same number of
>> instructions anyway. If Zihintpause is supported, we trade the nop from
>> the static branch for a div. If Zihintpause is unsupported, we trade the
>> jump from the static branch for (what gets interpreted as) a nop.
>
> Hi Samuel,
>
> I'm not sure whether it's correct to remove static branch usage from
> cpu_relax, but your report inspired my patch of constifying arguments
> of arch_static_branch() and arch_static_branch_jump() [1]. Could you
> please also test it?
>
> Thanks very much
>
> [1]https://lore.kernel.org/linux-riscv/20221006064028.548-1-jszhang@kernel.org/T/#u

Thanks.  IMO that's the better short-term fix, as that sorts out the 
build errors without dropping the div routine and we need the div 
routine to avoid regression on the old SiFive cores (like the one in the 
PolarFire SOC).  We can make a few improvements, though:

* If folks are worried about the performance of the static branch then 
  we can convert this over to an alternative.  It should be safe to 
  default to pause as it aliases a fence, it's just not as good at 
  slowing down the core.
* We can just drop the Zihintpause detection entirely and go with 
  .4byte/.insn to encode the pause.  That's essentially what we've dove 
  with the T-Head Zicbom stuff, but not sure it's worth it here because 
  Zihintpause is new.

>
>>
>> Fixes: 8eb060e10185 ("arch/riscv: add Zihintpause support")
>> Signed-off-by: Samuel Holland <samuel at sholland.org>
>> ---
>>
>>  arch/riscv/include/asm/hwcap.h          |  3 ---
>>  arch/riscv/include/asm/vdso/processor.h | 25 ++++++++++---------------
>>  2 files changed, 10 insertions(+), 18 deletions(-)
>>
>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
>> index 6f59ec64175e..b21d46e68386 100644
>> --- a/arch/riscv/include/asm/hwcap.h
>> +++ b/arch/riscv/include/asm/hwcap.h
>> @@ -68,7 +68,6 @@ enum riscv_isa_ext_id {
>>   */
>>  enum riscv_isa_ext_key {
>>  	RISCV_ISA_EXT_KEY_FPU,		/* For 'F' and 'D' */
>> -	RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
>>  	RISCV_ISA_EXT_KEY_MAX,
>>  };
>>
>> @@ -88,8 +87,6 @@ static __always_inline int riscv_isa_ext2key(int num)
>>  		return RISCV_ISA_EXT_KEY_FPU;
>>  	case RISCV_ISA_EXT_d:
>>  		return RISCV_ISA_EXT_KEY_FPU;
>> -	case RISCV_ISA_EXT_ZIHINTPAUSE:
>> -		return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
>>  	default:
>>  		return -EINVAL;
>>  	}
>> diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
>> index 1e4f8b4aef79..789bdb8211a2 100644
>> --- a/arch/riscv/include/asm/vdso/processor.h
>> +++ b/arch/riscv/include/asm/vdso/processor.h
>> @@ -4,30 +4,25 @@
>>
>>  #ifndef __ASSEMBLY__
>>
>> -#include <linux/jump_label.h>
>>  #include <asm/barrier.h>
>> -#include <asm/hwcap.h>
>>
>>  static inline void cpu_relax(void)
>>  {
>> -	if (!static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_ZIHINTPAUSE])) {
>>  #ifdef __riscv_muldiv
>> -		int dummy;
>> -		/* In lieu of a halt instruction, induce a long-latency stall. */
>> -		__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>> +	int dummy;
>> +	/* In lieu of a halt instruction, induce a long-latency stall. */
>> +	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>>  #endif
>> -	} else {
>> -		/*
>> -		 * Reduce instruction retirement.
>> -		 * This assumes the PC changes.
>> -		 */
>> +	/*
>> +	 * Reduce instruction retirement.
>> +	 * This assumes the PC changes.
>> +	 */
>>  #ifdef __riscv_zihintpause
>> -		__asm__ __volatile__ ("pause");
>> +	__asm__ __volatile__ ("pause");
>>  #else
>> -		/* Encoding of the pause instruction */
>> -		__asm__ __volatile__ (".4byte 0x100000F");
>> +	/* Encoding of the pause instruction */
>> +	__asm__ __volatile__ (".4byte 0x100000F");
>>  #endif
>> -	}
>>  	barrier();
>>  }
>>
>> --
>> 2.35.1
>>