Re: [PATCH v1 15/30] clk: starfive: Use regmap APIs to operate registers

[Conor Dooley]

On 23 October 2022 05:11:41 IST, Hal Feng <hal.feng at linux.starfivetech.com> wrote:
>On Wed, 12 Oct 2022 16:05:23 -0700, Stephen Boyd wrote:
>> Quoting Emil Renner Berthing (2022-10-05 06:14:44)
>> > > > @@ -295,11 +296,13 @@ static int __init clk_starfive_jh7100_probe(struct platform_device *pdev)
>> > > >         if (!priv)
>> > > >                 return -ENOMEM;
>> > > >
>> > > > -       spin_lock_init(&priv->rmw_lock);
>> > > >         priv->dev = &pdev->dev;
>> > > > -       priv->base = devm_platform_ioremap_resource(pdev, 0);
>> > > > -       if (IS_ERR(priv->base))
>> > > > -               return PTR_ERR(priv->base);
>> > > > +       priv->regmap = device_node_to_regmap(priv->dev->of_node);
>> > >
>> > > This is sad. Why do we need to make a syscon? Can we instead use the
>> > > auxiliary bus to make a reset device that either gets a regmap made here
>> > > in this driver or uses a void __iomem * mapped with ioremap
>> > > (priv->base)?
>> > 
>> > In my original code the clock driver just registers the resets too
>> > similar to other combined clock and reset drivers. I wonder what you
>> > think about that approach:
>> > https://github.com/esmil/linux/commit/36f15e1b827b02d7f493dc5fce31060b21976e68
>> > and
>> > https://github.com/esmil/linux/commit/4ccafadb72968480aa3dd28c227fcccae411c13b#diff-ffec81f902f810cb210012c25e8d88217ea5b4021419a4206d1fd4dd19edfce8R471
>> 
>> I think we should use auxiliary bus and split the driver logically into
>> a reset driver in drivers/reset and a clk driver in drivers/clk. That
>> way the appropriate maintainers can review the code. There is only one
>> platform device with a single reg property and node in DT, but there are
>> two drivers. 
>
>Yes, I agree that the reset driver and the clock driver should be split.
>However, I think using auxiliary bus is a little bit complicated in this
>case, because the reset is not a part of functionality of the clock in 
>JH7110. They just share a common register base address. I think it is 
>better to use ioremap for the same address, and the dt will be like
>
>syscrg_clk: clock-controller at 13020000 {
>	compatible = "starfive,jh7110-clkgen-sys";
>	reg = <0x0 0x13020000 0x0 0x10000>;
>	...
>};
>syscrg_rst: reset-controller at 13020000 {
>	compatible = "starfive,jh7110-reset-sys";
>	reg = <0x0 0x13020000 0x0 0x10000>;
>	...
>};
>
>What do you think of this approach? I would appreciate your suggestions.

No, the dtb checks will all start warning for this.
Aux bus is not that difficult, you can likely copy much of what I did recently in clk-mpfs.c
>
>Best regards,
>Hal