[PATCH] riscv: enable software resend of irqs

[Palmer Dabbelt]

On Thu, 13 Oct 2022 03:20:00 PDT (-0700), Marc Zyngier wrote:
> On Thu, 13 Oct 2022 02:13:50 +0100,
> Palmer Dabbelt <palmer at dabbelt.com> wrote:
>> 
>> On Mon, 10 Oct 2022 04:21:38 PDT (-0700), bjorn at kernel.org wrote:
>> > Conor Dooley <conor.dooley at microchip.com> writes:
>> > 
>> >> The PLIC specification does not describe the interrupt pendings bits as
>> >> read-write, only that they "can be read". To allow for retriggering of
>> >> interrupts (and the use of the irq debugfs interface) enable
>> >> HARDIRQS_SW_RESEND for RISC-V.
>> >> 
>> >> Link: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-pending-bits
>> >> Signed-off-by: Conor Dooley <conor.dooley at microchip.com>
>> > 
>> > Waking up an old thread. FWIW,
>> > 
>> > Reviewed-by: Björn Töpel <bjorn at kernel.org>
>> 
>> Thanks.  This look reasonable to me, not sure if the irqchip folks
>> have an opinion though?
>> 
>> In theory the PLIC isn't the only interrupt controller (and that spec
>> predates most of the implementations), but the SiFive PLIC derived
>> interrupt controllers have become a defacto standard and IIRC they're
>> the only thing shipping right now so I think it's OK to just stick
>> this in arch code.  We could mark it as "if SIFIVE_PLIC" or something,
>> but I don't know if that's worth doing.
>
> Setting it at the architecture level is at least consistent with what
> other arches are doing. If we need to fix it one day, we'll do it
> globally.

Works for me.

>
>> 
>> Either way, this isn't really my thing.  Happy to take it via the
>> RISC-V tree, but 
>> Acked-by: Palmer Dabbelt <palmer at rivosinc.com>
>> Tested-by: Palmer Dabbelt <palmer at rivosinc.com> # on QEMU
>
> Please take it directly, and feel free to add my
>
> Acked-by: Marc Zyngier <maz at kernel.org>
>
> to it.

Thanks, it's on riscv/for-next.

>
> Thanks,
>
> 	M.
>
> -- 
> Without deviation from the norm, progress is not possible.