[PATCH v8 1/3] riscv: mm: modify pte format for Svnapot
Jisheng Zhang
jszhang at kernel.org
Tue Nov 29 07:42:06 PST 2022
On Tue, Nov 29, 2022 at 10:49:46AM +0100, Andrew Jones wrote:
> On Mon, Nov 28, 2022 at 10:27:17AM +0800, panqinglin2020 at iscas.ac.cn wrote:
> > From: Qinglin Pan <panqinglin2020 at iscas.ac.cn>
> >
> > Add one static key to enable/disable svnapot support, enable this static
> > key when "svnapot" is in the "riscv,isa" field of fdt and SVNAPOT compile
> > option is set. It will influence the behavior of has_svnapot. All code
> > dependent on svnapot should make sure that has_svnapot return true firstly.
> >
> > Modify PTE definition for Svnapot, and creates some functions in pgtable.h
> > to mark a PTE as napot and check if it is a Svnapot PTE. Until now, only
> > 64KB napot size is supported in spec, so some macros has only 64KB version.
> >
> > Signed-off-by: Qinglin Pan <panqinglin2020 at iscas.ac.cn>
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 3b41165a8b10..1671938f2f81 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -394,6 +394,20 @@ config RISCV_ISA_C
> >
> > If you don't know what to do here, say Y.
> >
> > +config RISCV_ISA_SVNAPOT
> > + bool "SVNAPOT extension support"
> > + depends on 64BIT && MMU
> > + select RISCV_ALTERNATIVE
> > + default y
> > + help
> > + Allow kernel to detect SVNAPOT ISA-extension dynamically in boot time
> > + and enable its usage.
> > +
> > + SVNAPOT extension helps to mark contiguous PTEs as a range
> > + of contiguous virtual-to-physical translations, with a naturally
> > + aligned power-of-2 (NAPOT) granularity larger than the base 4KB page
> > + size.
> > +
> > config RISCV_ISA_SVPBMT
> > bool "SVPBMT extension support"
> > depends on 64BIT && MMU
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index b22525290073..15cda8f131aa 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -54,6 +54,7 @@ extern unsigned long elf_hwcap;
> > */
> > enum riscv_isa_ext_id {
> > RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
> > + RISCV_ISA_EXT_SVNAPOT,
> > RISCV_ISA_EXT_SVPBMT,
> > RISCV_ISA_EXT_ZICBOM,
> > RISCV_ISA_EXT_ZIHINTPAUSE,
> > @@ -69,6 +70,7 @@ enum riscv_isa_ext_id {
> > */
> > enum riscv_isa_ext_key {
> > RISCV_ISA_EXT_KEY_FPU, /* For 'F' and 'D' */
> > + RISCV_ISA_EXT_KEY_SVNAPOT,
> > RISCV_ISA_EXT_KEY_ZIHINTPAUSE,
> > RISCV_ISA_EXT_KEY_SVINVAL,
> > RISCV_ISA_EXT_KEY_MAX,
> > @@ -90,6 +92,8 @@ static __always_inline int riscv_isa_ext2key(int num)
> > return RISCV_ISA_EXT_KEY_FPU;
> > case RISCV_ISA_EXT_d:
> > return RISCV_ISA_EXT_KEY_FPU;
> > + case RISCV_ISA_EXT_SVNAPOT:
> > + return RISCV_ISA_EXT_KEY_SVNAPOT;
> > case RISCV_ISA_EXT_ZIHINTPAUSE:
> > return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;
> > case RISCV_ISA_EXT_SVINVAL:
> > diff --git a/arch/riscv/include/asm/page.h b/arch/riscv/include/asm/page.h
> > index ac70b0fd9a9a..349fad5e35de 100644
> > --- a/arch/riscv/include/asm/page.h
> > +++ b/arch/riscv/include/asm/page.h
> > @@ -16,11 +16,6 @@
> > #define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
> > #define PAGE_MASK (~(PAGE_SIZE - 1))
> >
> > -#ifdef CONFIG_64BIT
> > -#define HUGE_MAX_HSTATE 2
> > -#else
> > -#define HUGE_MAX_HSTATE 1
> > -#endif
> > #define HPAGE_SHIFT PMD_SHIFT
> > #define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
> > #define HPAGE_MASK (~(HPAGE_SIZE - 1))
> > diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> > index dc42375c2357..598958cbda50 100644
> > --- a/arch/riscv/include/asm/pgtable-64.h
> > +++ b/arch/riscv/include/asm/pgtable-64.h
> > @@ -74,6 +74,40 @@ typedef struct {
> > */
> > #define _PAGE_PFN_MASK GENMASK(53, 10)
> >
> > +/*
> > + * [63] Svnapot definitions:
> > + * 0 Svnapot disabled
> > + * 1 Svnapot enabled
> > + */
> > +#define _PAGE_NAPOT_SHIFT 63
> > +#define _PAGE_NAPOT BIT(_PAGE_NAPOT_SHIFT)
> > +/*
> > + * Only 64KB (order 4) napot ptes supported.
> > + */
> > +#define NAPOT_CONT_ORDER_BASE 4
> > +enum napot_cont_order {
> > + NAPOT_CONT64KB_ORDER = NAPOT_CONT_ORDER_BASE,
> > + NAPOT_ORDER_MAX,
> > +};
> > +
> > +#define for_each_napot_order(order) \
> > + for (order = NAPOT_CONT_ORDER_BASE; order < NAPOT_ORDER_MAX; order++)
> > +#define for_each_napot_order_rev(order) \
> > + for (order = NAPOT_ORDER_MAX - 1; \
> > + order >= NAPOT_CONT_ORDER_BASE; order--)
> > +#define napot_cont_order(val) (__builtin_ctzl((val.pte >> _PAGE_PFN_SHIFT) << 1))
> > +
> > +#define napot_cont_shift(order) ((order) + PAGE_SHIFT)
> > +#define napot_cont_size(order) BIT(napot_cont_shift(order))
> > +#define napot_cont_mask(order) (napot_cont_size(order) - 1UL)
> > +#define napot_pte_num(order) BIT(order)
> > +
> > +#ifdef CONFIG_RISCV_ISA_SVNAPOT
> > +#define HUGE_MAX_HSTATE (2 + (NAPOT_ORDER_MAX - NAPOT_CONT_ORDER_BASE))
> > +#else
> > +#define HUGE_MAX_HSTATE 2
> > +#endif
> > +
> > /*
> > * [62:61] Svpbmt Memory Type definitions:
> > *
> > diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgtable.h
> > index c61ae83aadee..af6174e3fd97 100644
> > --- a/arch/riscv/include/asm/pgtable.h
> > +++ b/arch/riscv/include/asm/pgtable.h
> > @@ -6,10 +6,12 @@
> > #ifndef _ASM_RISCV_PGTABLE_H
> > #define _ASM_RISCV_PGTABLE_H
> >
> > +#include <linux/jump_label.h>
> > #include <linux/mmzone.h>
> > #include <linux/sizes.h>
> >
> > #include <asm/pgtable-bits.h>
> > +#include <asm/hwcap.h>
> >
> > #ifndef CONFIG_MMU
> > #define KERNEL_LINK_ADDR PAGE_OFFSET
> > @@ -264,10 +266,45 @@ static inline pte_t pud_pte(pud_t pud)
> > return __pte(pud_val(pud));
> > }
> >
> > +static __always_inline bool has_svnapot(void)
> > +{
> > + return static_branch_likely(&riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_SVNAPOT]);
>
> I'm not sure if this should be likely or unlikely.
>
> > +}
> > +
> > +#ifdef CONFIG_RISCV_ISA_SVNAPOT
> > +
> > +static inline unsigned long pte_napot(pte_t pte)
> > +{
> > + return pte_val(pte) & _PAGE_NAPOT;
> > +}
> > +
> > +static inline pte_t pte_mknapot(pte_t pte, unsigned int order)
> > +{
> > + int pos = order - 1 + _PAGE_PFN_SHIFT;
> > + unsigned long napot_bit = BIT(pos);
> > + unsigned long napot_mask = ~GENMASK(pos, _PAGE_PFN_SHIFT);
> > +
> > + return __pte((pte_val(pte) & napot_mask) | napot_bit | _PAGE_NAPOT);
> > +}
> > +
> > +#else
> > +
> > +static inline unsigned long pte_napot(pte_t pte)
> > +{
> > + return 0;
> > +}
> > +
> > +#endif /* CONFIG_RISCV_ISA_SVNAPOT */
> > +
> > /* Yields the page frame number (PFN) of a page table entry */
> > static inline unsigned long pte_pfn(pte_t pte)
> > {
> > - return __page_val_to_pfn(pte_val(pte));
> > + unsigned long res = __page_val_to_pfn(pte_val(pte));
> > +
> > + if (has_svnapot() && pte_napot(pte))
>
> We've been burned with static branches inside heavily used inline
> functions before (see [1]). There's a series[2] that was meant to
> help with this. I haven't seen a refresh of that though.
>
> [1] https://lore.kernel.org/linux-riscv/20220922060958.44203-1-samuel@sholland.org/
> [2] https://lore.kernel.org/all/20221006070818.3616-1-jszhang@kernel.org/
I will send a refresh of [2] tomorrow.
Thanks
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