[PATCH 1/3] dt-bindings: timer: sifive,clint: add comaptibles for T-Head's C9xx

[Icenowy Zheng]

在 2022-11-21星期一的 12:17 +0800，Icenowy Zheng写道：
> T-Head C906/C910 CLINT is not compliant to SiFive ones (and even not
> compliant to the newcoming ACLINT spec) because of lack of mtime
> register.
> 
> Add a compatible string formatted like the C9xx-specific PLIC
> compatible, and do not allow a SiFive one as fallback because they're
> not really compliant.
> 
> Signed-off-by: Icenowy Zheng <uwu at icenowy.me>

Could this patch get applied individually?

I want to drop the practice of the latter two patches and send new
RFCs, and this patch is a dependency of some OpenSBI patch.

> ---
>  Documentation/devicetree/bindings/timer/sifive,clint.yaml | 8
> ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git
> a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> index bbad24165837..aada6957216c 100644
> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
> @@ -20,6 +20,10 @@ description:
>    property of "/cpus" DT node. The "timebase-frequency" DT property
> is
>    described in Documentation/devicetree/bindings/riscv/cpus.yaml
>  
> +  T-Head C906/C910 CPU cores include an implementation of CLINT too,
> however
> +  their implementation lacks a memory-mapped MTIME register, thus
> not
> +  compatible with SiFive ones.
> +
>  properties:
>    compatible:
>      oneOf:
> @@ -29,6 +33,10 @@ properties:
>                - starfive,jh7100-clint
>                - canaan,k210-clint
>            - const: sifive,clint0
> +      - items:
> +          - enum:
> +              - allwinner,sun20i-d1-clint
> +          - const: thead,c900-clint
>        - items:
>            - const: sifive,clint0
>            - const: riscv,clint0